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CONTROL DATA® 1700 

COMPUTER SYSTEM 

1704-A/B, 1705-A, 170S-A 
(Including Standard Options 
10040-10043), AA101-A/B 


DIAGRAMS & 

CIRCUIT DESCRIPTION 
CARD PLACEMENT 


CONTROL pm 

CO R P ORATION 


CUSTOMER ENGINEERING MANUAL 



RECORD of REVISIONS 


REVISION 


NOTES 


(10-22-65) 


( 1 - 21 - 66 ) 


(8-19-66) 


(12-23-66) 


(12-23-66) 


(12-23-66) 


(12-23-66) 


(3-16-67) 


G 


(3-16-67) 


H 


(3-16-67) 


(7-28-67) 



(7-28-67) 


(7-28-67) 


N 


(7-28-67) 


This edition obsoletes all previous editions. 


This revision includes prerelease revisions through No. 5. All pages in Part 1 and page 117 in 


Part 2 were changed. 


Publications Change Order 14476 (manual released). Complete revision to circuit description 


command timing charts deleted. This manual is correct through the following Product 


Designation levels: 1703-A02, 1704-A12, 1705-A02, 1708-A01, 1709-A01, Standard Options 


10040-A01, 10041-A01, 10042-A01, and 10043-A01, This edition obsoletes all previous editions. 


Change Order 14535, no Product Designation change. Page 143 revised. 


Field Change Order 14750, new Product Designation 1704-A13. Page 145 revised. 


Field Change Order 14392, new Product Designation 1704-A14. Pages 15, 17, and 19 revised. 


Publications Change Order 15272, no Product Designation change. Pages 7, 9, 11, 17, 23, 27, 


29, 31, 35, 39, 47, 49, 51, 69, 73, 75, 77, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 102, 


103, 105, 107 and 135 revised. 


Field Change Order 14912, (MDR 15) new Product Designation 1704-A15. No change to this 


manual. 


Field Change Order 15192, new Product Designation 1704-A16, (MDR 16) no change to this manual , 


Field Change Order 15688, new Product Designation 1704-A.17, (MDR 17). Pages 18, 19, 101, 
141 and 155 revised. 


Change Order 15843, no Product Designation change. Page 7 revised. 


Publications Change Order 16028, no Product Designation change. Pages 75, 78.4, 80, 81, 108, 


131, and 133 revised. 


Field Change Order 16043, new Product Designation 1704-A18 (MDR 18). No change to this 


manual. 


Change Order 16088, no Product Designation change. Page 149 revised. 


Field Change Order 16267, new Product Designation 1704- A1 9 (MDR 19), Page 153 revised. 


Field Change Order 16344, new Product Designation 1704-A20 (MDR 20). No change to this manual 


Field Change Order 16482, new Product Designation 1704-A21 (MDR 21). Pages 103 and 105 


revised. 


Field Change Order 16531. new Product Designation 1704-A22 (MDR 22). Pages 75 and 153 


revised. 


Field Change Order 16615, new Product Designation 1704- A2 3. No change to this manual. 


Field Change Order 16529, no Product Designation Change. Page 149 revised. 


Pub No. 60152700 

© 1965, 1966, 1967, 1968, 196 9, 1970, 1971 
by Control Data Corporation 

Printed in United States of America 


Address comments concerning this 
manual to: 

Control Data Corporation 
Technical Publications Department 
4201 North Lexington Avenue 
St, Paul, Minnesota 55112 

or use Comment Sheet in the back of 
this manual. 


FORM CA230 REV. 
































































RECORD of REVISIONS (CONT'D) 

REVISION 

NOTES 

P 

Publications Change Order 17060, no Product Designation change. Pages 3, 7, 15, 17, 19, 21, 23, 29, 

(7-28-67) 

47, 49, 51, 55, 56. 0, 80. 81, 119, 153 and 155 revised. 

R 

Field Change Order 16817 (MDR 23, new Product Desitnation 1704- A24. Pages vi, 3, 13, 19, 20. 1, 

(9-1-67) 

20. 2, 23. 39, 41, 69, 99. 105, 107, 127, 129, 131, 133, 135, 137, 139, 141, 143, 145 and 147 revised. 

s 

Field Change Order 17320 (MDR 24), new Product Designation 1704-A25. Pages 31, 35, 43, 53, 

(10-6-67) 

57,71, 77, 107 and 145 revised. 

(3-7-68) 

Field Change Order 17750, new Product Designation 1704-A26, No change to this manual. 

T 

Field Change Order 18378, new Product Designation 1704- A27. Pages 81, 103, 145 and 147 

(3-7-68) 

revised. 

u 

Publications Change Order 19012, no Product Designation change. Pages 3, 67, 133 and 141 

(3-8-68) 

revised. 

V 

Field Change Order 19097, new Product Designation 1704- A28. Page 135 revised. 

(8-6-68) 


w 

Engineering/ Publications Change Order 19375, no Product Designation change. Pages 81, 103, 

(8-6-68) 

105, 145 and 147 revised. 

Y 

Engineering Change Order 20253, Pages 19, 21, 35, 43, 51, 59, 61, 63, 65, 73, 81, 121 and 123 

(8-6-68) 

revised. 

(12-4-68) 

Manual revised; includes Field Change Order 19317, equipment level 1704-A29. No change to 


this manual. 

Z 

Manual revised; includes Field Change Order 20893, equipment level 1704-A30. 

(12-4-68) 

Pages 135 and 139 revised. Added pages 145, 147 and 149. 

AA 

Manual revised; includes Engineering Change Order 21046. Publication Change only. Cover and 

(12-4-68) 

Title Page revised. Pages vi, 4, 12, 17, 19, 22, 24, 31, 35, 39, 48, 57, 59, 61, 63, 65, 69, 75, 80, 99, 103, 


105, 117, 125, 127, 133, 151 and 153 revised. Page 106 was added. Added 1704-B information 


at equipment level BOl. 

(4-10-69) 

Field Change Order 20971, equipment level 1704-A30. No change to this manual. 

AB 

Manual revised; includes Engineering Change Order 21570, publication change only* Pages 139, 

(4-10-69) 

141 and 149 revised. Added page 148. 

AC 

Manual revised, includes Field Change Order 21048, equipment level 1704- AO 1 through A31, 

(5-8-70) 

1704-B01 through B02. Pages 31 and 35 revised. 

AD 

Manual revised, includes Engineering Change Order 22284. Page 141 revised. 

(5-8-70) 


AE 

Manual revised, includes Engineering Change Order 22477. Pages 135 and 145 revised. 

(5-8-70) 


AF 

Field Change Order 22196. No change to this manual. 

(5-8-70) 


AG 

Manual revised, includes Engineering Change Order 24078. Page 147 revised. 

(5-8-70) 


AH 

Manual revised, includes Engineering Change Order 24271. Pages 155 through 172 added. 

(5-8-70) 


AJ 

Manual revised, includes Engineering Change Order 24238. Page 147 revised. 

(5-8-70) 


AK 

Manual revised, includes Engineering Change Order 25071. Page 153 revised. 

(5-8-70) 


AL 

Manual revised, includes Field Change Order 25377, equipment level 1704-A01/B01 through 

(9-15-70) 

A32/B03. Pages 11,57 and 69 changed. 

AM 

Manual revised, includes Engineering Change Order 26170, publication change only. Pages 7 

(9-15-70) 

and 49 revised, pages A-1 through A-28 added. 




Pub. No. 60152700 


FORM CA 230-2 

















































































RECORD of REVISIONS (CONT’D) 

REVISION I NOTES 

AN Engineering Change Order 26078; no change to this manual. 

(6-3-71) 


AP Manual revised; includes Engineering Change Order 27989, publication change only. Pages 7, 11, 

(6-3-71) 25, 26, 49, and Comment Sheet revised. 



Pub. No. 60152700 


FORM CA230-: 













FOREWORD 


The 1700 Customer Engineering Manual provides logic diagrams and circuit 
descriptions of the CONTROL DATA'*' 1700 Computer System. This manual 
contains information on all units contained in the main computer cabinet with 
the exception of the Basic Peripheral Equipment, which is in Publication 
Number 60164200. 

The circuit descriptions and diagrams are arranged to give a general continuity 
of logic flow. Thus, the Clock and Timing controls are given first, followed by 
the Register groupings. Adder /Shifter, etc. A special reference is made to the 
Command Timing sequences. These sequences give the detailed timing of each 
instruction. Thus, the Command Timing sequences logically interconnect various 
diagrams on a timed sequence basis. Refer to the 1700 Computer System Command 
Timing Charts, Pub. No. 60194500. 

The logic diagram symbol description and the block diagram description precede 
the detailed circuit descriptions. The Logic Diagram Symbol section lists each of 
the standard logic symbols used on the diagrams and a brief description of their 
meaning and use. 


*Registered trademark of Control Data Corporation 


iii 


Rev. A 




CONTENTS 


Part 1. Diagrams 
Main Computer 

Block Diagram 1 

Clock - Normal Speed 3 

Clock - Slow and Fast 5 

Timing Chain 7 

Sequence Controls 9 

Cycle Control 11 

Addressing Controls 13 

Manual Controls (Sheet 1) 

(Register Selection and Clear 
Controls) 15 

Manual Controls (Sheet 2) 

(Switch and Indicator Drivers) 17 

Manual Controls (Sheet 3) 

(Test Mode and Run/Step) 19 

Manual Controls (Sheet 4) 

(Typical Register Display) 21 

F Register 23 

Function Translations (Sheet 1) 25 

Function Translations (Sheet 2) 27 

Function Translations (Sheet 3) 29 

A Register 31 

Q Register 33 

A, Q Fan-Out 3 5 

P Register 37 

X Register 3 9 

Y Register 41 

Y Decrementer and Skip FF 43 

Adder Controls (XR and LP) 45 

Adder Controls (Shift) 47 

Adder Gate Controls (Augend) 49 

Adder Gate Controls (Addend) 51 

Adder /Shifter Fan-In 
Augend Gates 53 

Adder /Shifter Fan-In 
Adder Gates 55 


Group 0 of Adder 57 

Adder /Shifter Groups 0 and 1 59 

Adder/Shifter Groups 2 and 3 61 

Adder /Shifter Groups 4 and 5 63 

Adder/Shifter Groups 6 and 7 65 

Optional Mask and Interrupt 
Registers and Receivers 67 

Program Protect and Interrupt 6 9 

Mask Register and Interrupt 
Priority 71 

Shift , MUI,and DVI Controls 73 

AQ I/O (Part 1) 75 

AQ I/O (Part 2) 77 

Storage 

Block Diagram 1700 Storage 79 

S Register 81 

Z Register (Stages 0 and 1) 83 

Z Register (Stages 2 and 3) 85 

Z Register (Stages 4 and 5) 87 

Z Register (Stages 6 and 7) 89 

Z Register (Stages 8 and 9) 91 

Z Register (Stages 10 and 11) 93 

Z- Register (Stages 12 and 13) 95 

Z Register (Stages 14 and 15) 97 

Z Register (Stages 16 and 17) 99 

Storage Interface 101 

Storage Timing Chain 103 

Storage Timing and Control 
(Sheet 1) 105 

Storage Timing and Control 
(Sheet 2) 107 

X and Y Drive Decks 109 

Inhibit Drive Decks 111 

Transfers 

Addressing Modes 113 

Addressing Modes 115 


V 


Rev. A 



CONTENTS (Cont^d) 


STO Transfers 117 

REG Transfers 119 

ROP Transfers 121 

B Cycle Transfers 123 

C Cycle Transfers® 125 

Power and Cabling 

Power Distribution, Vertical 

Auxiliary Cabinet 127 

Power Control Panel 129 

Monitor Panel 131 

Power Distribution Box 

Schematic 133 

I Wiring Diagram 135 


Logic and Memory Power 

Supplies 137 

M-G Assemblies 139 

400 Cycle Terminator Power 

Supply 141 

Cabling Diagram 143 

1704- B Cabinet Power Distribution 145 

Power Supplies 147 

Power Distribution Box 

Schematic 149 


Part 2. Card Placement 

Maintenance 1-55 


Rev AH 


vi 



PART 1 


DIAGRAMS AND CIRCUIT DESCRIPTION 




MAIN COMPUTER 




LOGIC DIAGRAM SYMBOLS 


Two signals, a logical ”0" and a logical "l", are the possible input or output 
conditions of a circuit. By convention, "l" is considered "up” and "O" is con- 
sidered "down" on a timing chart, for example. Detailed descriptions of logic 
symbols and their associated electronic representations are contained in the 
Printed Circuits Manual, Vols. 3 and 4. 

STANDARD LOGIC SYMBOLS 

The 1700 Computer logic is mainly composed of the CONTROL DATA 6000 
Series printed circuit modules. Standard logic diagram symbols for this type 
of printed circuit modules are inverters, test points, flip-flops, and twisted 
pair line drivers. 

INVERTERS 

An inverter is a logic element which provides an output that is an inversion of 
its input. When an inverter receives more than one input, "O's" take pre- 
cedence over "I's" and drive the output of the inverter to "l". Because all of 
the several inputs have to be "l" to drive the output of the inverter to a "0", 
the inverter may be considered an inverting AND (or NAND) gate when more 
than one input is present. Logic diagrams show the basic inverter as an arrow 
into either a circle or a square (see Figure 1). Both symbols represent the 
same electronic circuit and have the same logical interpretation. In a logic 
sequence of inverters, circle and square symbols are usually alternated as an 
aid in tracing signals, e.g., a "l" output from a square symbol implies a "l" 
output from subsequent squares in the logic chain if each symbol in the chain has 
only one input. 

Acceptable conventions for showing multiple inputs and outputs are given in 
Figure 2. Note that the output of inverter A is "O" only if inputs X, Y, and Z 
are all "l". The multiple outputs are identical. 

Figure 3 shows an example of an inverter network. Because multiple outputs 
are identical. Figure 4 shows only one arrow in cases where an inverter (A) 
serves as the single input to several succeeding inverters. In more complex 
inverter networks, multiple arrows are used (B to C and D because B is not 
the only input to C or D). 



Figure 3. Inverter Networks 

TEST POINTS 

A test point performs no logic function. Logic diagrams show the test point 
as a triangle (see Figure 4). Test points are numbered from 1 to 6. 

-j- -t 

Figure 4. Test Point Symbols 

FLIP-FLOPS (FF) 

The flip-flop is composed of two inverters and functions as a storage device 
with two stable states designated as set and clear (see Figure 5). The flip- 
flop is set when the set output (B) is a "l" and clear when it is a "O". Note 
that the input (A) must be "O" to set the flip-flop, and (C) must be "O" to 
clear it. 



O 




^ DENOTES SPECIAL 
TEXT REFERENCE 


Figure 1. Inverter Symbols 
Figure 2. Multiple Inputs /Outputs 


Figure 5, Flip-Flop Symbol 


WIRE TAB DESIGNATIONS 

Wire tab designations written next to a 
pin indicate where in the drawings the 
pin is connected, 3, 5, 7 - C37 - 6 
indicates a connection with pin 6 of 
module C37, found on pages 3, 5, and 
7. See Figure 5.1 . 


PAGE LOCATION PIN 

\ 1 / 

3,5,7 C37 6 

(X IN PLACE OF PIN NUMBERS 
DENOTES GROUND) 

Figure 5.1 . Wire Tab Designations 


iii 
Rev. A 



TWISTED PAIR DRIVERS 

A Line Driver circuit transmits logic signals from one module to another. Modules 
are connected by twisted-pair lines. The standard square or circle represents the 
twisted-pair driver. However, the output of the square or circle connects to a pin 
of the module. The pin is then wired to a pin on another module (see Figure 6). 

The ground wire of the pair is wired to the connector ground bus of each module. 

The pins are represented by small circles and are numbered from 1 to 28. (Pins 29 
and 30 are ground and +6 volts, respectively, and generally are not shown in logic 
diagrams.) The module location is shown above the card, and the module type is 
denoted in the upper right-hand corner. 



Figure 6. Twisted-Pair Line Driver 


RECEIVER/ TRANSMITTER CIRCUITS 

The Receiver and Transmitter circuits detect and transmit signals from and to I/O 
interface respectively. The Receiver and Transmitter circuits are modifications of 
the standard 3000 Series circuits of the same name. These circuits are contained 
on a printed circuit module along with the standard inverter circuits. 

Figures 7 and 8 shows that Receiver and Transmitter circuits are represented by the 
square symbol with an "R" or "T" respectively. The two inputs to the receiver 
are each connected to two pins on the module. 

In Figure 7, a "l" input to R is inverted, causing a "1" output from pin 6 and a ”0" 
output from pin 13. Thus, with a "1" input, the Receiver circuit produces both True 
and Not outputs. 

The Transmitter circuit receives a "1" input signal from a standard inverter or FF 
and transmits a "1” output signal to the I/O interface. In Figure 7, a "1" input to 
pins 7 and 9 causes a "1" output from T and thus to the I/O line. 


INPUT 
FROM I/O 
INTERFACE 




TO I/O 
INTERFACE 


Figure 7. Receiver /Transmitter Circuit Examples 


RECEIVER 


TRANSMITTER 


lli. 


EACH STAGE OF THE ZS MODULES CONTAIN 

FOUR EXTERNAL PINS WITH INTERNAL CONNECTIONS 

Figure 8. Z5 Transmitter/Receiyer Module 
SPECIAL CIRCUITS 

In addition to the standard symbols, the diagrams also use symbols representing 
special nonstandard circuits. The symbols for these circuits along with a brief 
description are given below. 

Special variations of the standard building block are indicated by the symbols shown 
on Figure 9. The symbol and schematic for the corresponding special circuit are 
shown on the applicable logic diagram and also on the module schematic in the 
Printed Circuits Manual. 

^ Hi] H ® 


Figure 9. Special Circuits 


CAPACITIVE DELAY CIRCUITS 

Capacitive Delay circuits delay input "1" signals a prescribed time before issuing 
an output "1" signal. The 1700 uses both fixed and variable delay circuits. Figure 10 
shows examples of both types. The delay time of the circuit and capacitor value are 
listed beside the capacitor symbol. The variable potentiometer enables adjustment of 
the delay time of the circuit within certain limits. 



FIXED DELAY VARIABLE DELAY 


Figure 10. Capacitive Delay Circuits 


iv 

Rev. A 








BLOCK DIAGRAM 


The block diagram shows the main circuits in the 1704 Arithmetic and Control 
portion of the CONTROL DATA 1700 small industrial computer. The I/O 
and memory interfaces are indicated. 

As shown, the 1704 consists mainly of registers, the adder/shifter network, 
and control circuits. In general, the registers contain quantities for some 
period of time. When the quantities require an Arithmetic, Logical, or 
Transfer operation, they are transmitted through the adder /shifter network. 

The adder/ shifter combines the quantities with one another in a Logical or 
Arithmetic operation, operates on them independently as in a shift, or simply 
serves as a path for the contents of one register to transfer to another register. 
Thus, the adder /shifter serves as the main path for all Arithmetic, Logical, 
or Inter-Hegister Transfer operations. 

MAIN REGISTERS 

The function of the main registers shown on the block diagram is briefly 
described in the following paragraphs. 

Z REGISTER 

The 18-bit Z register temporarily stores all data words being read from or 
written into storage. Bits 16 and 17 are not part of the data but are the program 
protect and parity bits respectively. Control operates on these bits independently 
from the data bits. 

In a Read Memory operation, the 16 data bits transfer to the X register. In 
a Write operation, the data bits to be written are transferred from X to Z 
register. 

X REGISTER 

The 16-bit X register holds the data bits transferring to or from the Z register. 
This register holds one of the parameters in most Arithmetic operations. When 
the X register contains an instruction, the high- order 8 bits transfer to the F 
register for translation. 

F REGISTER 

The 8-bit F register contains the instruction code and/or addressing mode 
bits. The translation of these bits direct the execution of the instructions, 

Y REGISTER 

The 16-bit Address register contains the storage address for transfer to the 
S register during a storage reference. The Y register in conjunction with the 

Y Decrementer also functions as a counter during the multiply and shift 
instructions. The Y register temporarily stores the incomplete addresses 
during address modification and the final effective address when modification 
is complete. 


S REGISTER 

The 15-bit Storage Address register contains the effective storage address 
transferred from the Y register or from the external storage access. All 
address selection for internal storage access is controlled by the contents 
of the Y register. 

P REGISTER 

The 15-bit P register contains the program address of the instruction currently 
being executed. In the later stages of instruction execution, except in certain 
Jump and Skip instructions, the P register is advanced by adding +1 in the 
adder /shifter network for referencing the next instruction. 

A REGISTER 

The 16- bit A register functions as the principal register in most Arithmetic 
and Logical operations. 

Q REGISTER 

The 16-bit Q register serves as the auxiliary register in most Arithmetic 
and Logical operations. 

MASK REGISTER 

The 16- bit Mask register contains the interrupt mask bits. Each bit in the Mask 
register corresponds to a particular interrupt line. In order for a particular 
type of interrupt to be recognized when it occurs, the corresponding bit in the 
Mask register must be a "1". 


ADDEND /AUGEND GATES 

The addend/augend gates serve as the input gate control for the adder /shifter. 
In most Arithmetic, Logical, or Register Transfer operations, one input is 
selected by the addend gates and one by the augend gates. Thus, four inputs 
are applied to addend and augend gates respectively. 


ADDER/SHIFTER 

The adder/ shifter performs all Arithmetic and Logical operations on the 
register contents. The adder/ shifter also serves as the transfer path for all 
Inter-Register Transfer operations. 


MAIN CONTROL 

The main control circuits are shown on the right side of the block diagram. 


V 

Rev. A 



MANUAL CONTROLS 

The manual controls consist of the start, stop, manual set, and indicator control 
circuits. Thus, the manual controls initiate all start, stop, and manual selection 
operations in the computer. 

CLOCK 

The clock circuit produces 4- phase, 2 5- nsec clock pulses which form the timing 
base for all control operations in the computer. 

TIMING CHAIN 

With an input from the clock and manual controls, the timing chain produces a series 
of eight controlled 25-nsec timing pulses at 50~nsec intervals. 

SEQUENCE CONTROL 

The sequence control circuit controls the mode of operation for the execution of a 
given instruction. There are five general modes of operation: 

1) Read Next Instruction (RNI) 

2) Address Mode (ADR) 

3) Read Operand (ROP) 

4) Store Operand (STO) 

5) Register Transfer Mode (REG) 


The execution of an instruction may pass through two or more modes of operation. 

All instructions begin in the RNI mode and then enter one or more of the other modes 
in sequence. 

CYCLE CONTROL 

Three main timing cycles control instruction operation: the A cycle, B cycle, and C 
cycle. The A cycle begins with an initial start or resume from storage. The A cycle 
enables such operations as addlressing, initial register transfers, etc. 

The B cycle is initiated immediately after the A cycle except in multiply, divide, and 
shift operations. The B cycle initiates storage operations. 

The C cycle begins after the A cycle and performs multiply, divide, or shift cycle 
iterations. 

REGISTER TRANSFER CONTROLS 

This circuit controls the transfer of registers in the computer based on the cycle, 
sequence mode, and instruction being executed, 

ADDRESSING CONTROL 

This circuit controls the modification of the address in storage reference instruction. 
The addressing control circuit receives inputs from cycle control, sequence control, 
and the address control bits in the instruction^. 


vi 

Rev. A 









MASTER CLOCK - NORMAL SPEED 


Timing in the 1700 is controlled by a 4-phase master clock* Four. 25-nsec 
pulses are issued each minor cycle to conti’ol movement of data and instructions. 

The master clock oscillator consists of a TD module and a V50 module. To form 
the 25-nsec pulses, a pulse from the TD is ANDed with a similar pulse which has 


been delayed and inverted by the V50. The result is a series of pulses (primary 
clock) which are fanned out through V31 and TC modules to be used as timing 
control. 


I I I 


1 

J 

"o" 

n 

L n 

1 

1 

1 

n 

1 

1 I 1 

1 i 1 

n 

J 


n 


4 - PHASE CLOCK 
(FROM FAN-OUT) 

1 

— 1 

i 


j 

1 

n 1 

n 

J 

n 


t75 1 1 1 I I I I [ 


2 

Rev. A 









MASTER CLOCK - SLOW AND FAST 


The master clock pulse rate may be increased or decreased by substitution of The V52 module has a shorter oscillator loop which increases the clock speed by 

a V51 or V52 in place of a V50 module. The V51 module has a longer oscillator shortening the wires between the TD and V52 module, 

loop than the normal V50 module. 

The V51 and V52 modules are for maintenance only and can not be used for normal 
computer operation. 



„ 4 

Rev. aA 



OSCILLATOR LOOP 


OSCILLATOR LOOP 











TIMING CHAIN AND CONTROL 


The timing chain for the 1700 Computer consists of two V69 modules. Each 
module contains four FFs connected together, forming a chain of eight FFs 
(H00-H07). Each FF is gated by a clock pulse. As a ”1" passes down the chain, 
each FF is set for 75 nsec. The FFs alternately set at tOO and t50 and clear at 
t25 and t75, thus overlapping each other by 25 nsec. Normally, the total cycle 
time for one pass of the timing chain is 400 nsec. The exception is explained 
below under Short Cycle 1. 

The timing chain enables the V000-V350 25-nsec pulses. The V pulses occur at 
too and t50, simultaneous to the setting of the timing chain FFs. 

T pulses, V pulses, and H--FFs control computer timing, with the exception of 
storage control. Storage control uses a separate timing chain consisting of K--FFs. 

Shown on the top of page 7 are a number of fan-outs for the timing chain. The fan- 
outs are shown as partial modules, because they are included on modules of un- 
related logic. 

SHORT CYCLE 1 

During Multiply and Shift instructions, time 250 occurs 100 nsec early. This 
sequence occurs only during the C cycle when the Short Cycle 1 (SCI) signal is 
present. FF H02 sets at time 100, but an SCI signal blocks the setting of HO 3 at 
time 150. Instead, the H02 enable leaves module V69 through pin 5 and enters 
the second V69 module at pin 25. The SCI signal at pin 23 enables the setting of 
H05 at time 250. FFs H03 and H04 are not set during the SCI condition. 

START TIMING CHAIN 

Initially, the timing chain starts by enabling the RUN /STEP or TEST MODE 
switches. The Run/ Step or Test Mode switch sets the Go 1 FF on module 
V49, p. 19. The Go 2 FF (module V55) sets and starts the timing chain if the 


Go 1 signal is present and the Display FF set. The Go 2 FF sets at time 25 and 
the timing chain starts 75 nsec later at time 00. 

RESTART TIMING CHAIN 

There are three main gates for restarting the timing chain without using the 
manual switches. These are the conditions for restarting the computer during 
program control. 

1) Stop 2 FF clear and Storage Resume signal present 

2) H07 (^) [b cycle + (IM.OP. ) (ROP)] 

or 

3) H05 and SC 2 

or 

4) Go 2 FF set 

The first condition restarts the timing chain after a storage reference. The 
second condition restarts the timing chain at the end of the B cycle if no storage 
reference is initiated or at the end of the A and C cycles. The third condition 
occurs during the C cycle of a Shift instruction. The SC 2 signal blocks H06 and 
H07 and restarts the timing chain early. 

SET F REGISTER 

Output pins 3 and 5 of module V55 enable the setting of the F register under the 
following conditions: 

1) Sweep + Enter (RNI) (Go 2) 

2) Sweep + Enter (RNI) (Resume) (Stop 2) 

The Run/Step or Test Mode switches enable the first condition and the storage resume 
enables the second condition. 


6.1 

Rev. A 













SEQUENCE CONTROLS 


There are five modes of operation in the 1700 which enable a general series of 
commands for groups of instructions. 


1) 

RNI 

Read Next Instruction 

2) 

ADR 

Addressing 

3) 

REG 

Register Transfer 

4) 

ROP = 

Read Operand from Storage 

5) 

STO 

Store Operand in Storage 


RNI 

The command timing for all instructions starts in the RNI mode. During RNI, 
the instruction code transfers from the Z register to the X register and from 
the X register to the F register. While in the F register, the instruction code 
is translated to determine whether it is addressable. If it is addressable, the 
ADR mode is initiated. If it is not addressable, the REG mode is initiated. A 
block diagram on the lower portion of the diagram shows the possible sequence 
paths . 

The RNI Control FF is located on module V71 and has five main setting gates. 

If any one of the gates is satisfied, the RNI mode is enabled. 

1) Master Clear - before starting a program. 

2) (B150) (STO) - after storing an operand 

3) (B150) (ROP 2) [raO (ROP)]- after reading an operand (except Replace 
Add One instruction) 

4) (B150) (ADR) jjjMP) (End ADR)J - after addressing (Jump instruc- 
tion only) 

5) (B150) [[(REG) (SPB + CPB + EXI + INT)[] - after REG mode (except 
Set/Clear Program Protect, Exit Interrupt, and interrupt during REG) 

The RNI Control FF clears at time 150 of the B cycle (B150) if none of the 
setting gates are satisfied. 

ADR 

Instructions which are read from or written into storage use the ADR mode. The 
only exceptions are Set/Clear Program Protect, Exit Interrupt, and Interrupt 
During REG mode in which the address is already determined. During the ADR 
mode, storage is always requested. 


The ADR Control FF is located on module V70 and has one main setting gate 
which enables the ADR mode. 

(RNI) (A050) (F i 0) [(Protect Fault) (Sweep + Enter)] - after reading 
next instruction, if F 0, not addressing a protected instruction from an 
unprotected instruction and Sweep or Enter switch not enabled. 

Storage is referenced when the Sweep switch is on but not during an ADR mode. 

The ADR Control FF clears at time V300, providing the RNI, ROP, or STO 
Control FF is set. The setting of the two control FFs overlap but the mode remains 
ADR until the ADR FF clears. 

REG 

Instructions which do not reference storage for reading or writing operands are 
considered as being in the Register Transfer mode (REG). During REG, computer 
control enables control FFs, enables register transfers, updates the address for 
the next instruction, and requests storage. The exceptions are Set/Clear Program 
Protect, and Exit Interrupt, where the REG mode is followed by an ROP mode. 

During the REG mode of these instructions the address is modified and storage 
requested. The address for the next instruction is updated during the ROP mode. 

If the computer is in REG mode when an interrupt occurs, the STO FF sets and 
enables STO mode. 

The REG control FF is located on module V70 and has one main setting gate 
which enables the REG mode. 

(Protect Fault) + [jRNI)(A050)( [Sweep + Enter] + F = 0)J 

A Protect Fault signal enables the REG mode and treats the instruction as a 
nonprotected "Pass" with REG mode updating the address of the next instruction. 

The Sweep or Enter signal enables the REG mode during RNI, and the next 
address is updated without using ADR mode. If the upper 4 bits of the instruction 
equal zero (F = 0) the REG FF sets during the RNI mode. 

The REG Control FF clears at time B300 whenever the set input is not satisfied. 

8.1 

Rev. A 



SEQUENCE CONTROLS (Cont'd) 


ROP 

The ROP mode applies to instructions which read operands from storage and 
the EXI, SPB, and CPB instructions. 

The ROP Control FF (ROP l)is located on module V64 and has two main setting 
gates. The ROP 2 FF on module V71 provides a delay which prevents the RNI 
FF from setting at the same time (B150) as ROP or STO. The setting gates for 
ROP I are as follows: 

1) ( B150 ) ( ADR) [( End ADR + STQ + RTJ + STA + SPA) (End ADR) 

(JMP + End ADR) 3 - not a Store in struction, end of addressing, and not 
a Jump instruction. The End ADR condition is not considered in the 
setting of the FF. 

2) (B150) (INT) [rEG (SPB + CPB + EXI)] - an interrupt during REG 
mode enables STO. 

The ROP 1 FF clears at time B300 if the RNI or STO 1 FF is set. The normal 
sequence path is from ROP to RNI, as a Replace Add One instruction is 
necessary to set STO. 


STO 

The STO mode applies to instructions which write operands into storage and 
interrupts occurring during the ADR or REG modes. 

The STO Control FF (STO l)is located on module V64 and has two main setting 
gates. The STO 2 FF on module V71 provides a delay which prevents the RNI 
FF from setting at the same time (B150) as ROP or STO. The setting gates for 
STO lare as follows: 

1) (B150) (ADR + REG) [(End ADR) (STQ + RTJ + STA + SPA) + INT] - 
interrupt enables STO 1 from ADR or REG mode, other instructions 
come from ADR mode only. 

2) (B150) (ROP 2 (RAO) - Replace Add One instruction came from ROP 
mode. It reads from and then writes into storage. 

The STO IFF clears at time B300 if the RNI FF is set. The computer always 
initiates an RNI mode after writing into storage. 


8.2 

Rev. A 















One pass down the timing chain is considered a cycle. The 1700 Computer has 
three unique cycles. 

1) A cycle (storage resume) 

2) B cycle (storage request) 

3) C cycle (iterative) 

The normal cycle sequence is resume, request, resume, request, etc. or 

A ^ B ^ A -- B, etc. 

The Multiply, Divide, and Shift instructions use a C cycle in addition -to the A and 
B cycles. The C cycle is iterative because the computer stays in the C cycle 
until shifting for that particular instruction is complete. The C cycle occurs 
between the resume and the next request. 

A B 

A and B cycles are always 400 nsec long. C cycles are either 200, 300 (short 
cycle) or 400 nsec long. Shift C cycles are 200 nsec long and multiply C cycles 
are 300 nsec long until the last C cycle (YOO-04 = 0), which is 400 nsec long. 

All C cycles for divide are 400 nsec long. 

Cycle control, sequence control, and timing chain times are combined to 
enable specific conditions in command timing. For example, an instruction 


CYCLE CONTROL 


may have two or more B cycles and time 100s. The sequence mode combined 
with BlOO enables a unique condition such as ADR (BlOO), ROP (BlOO), or 
RNI (BlOO). 

The three modules below contain two Control FFs and the fan-out for each cycle. 
The Early Cycle FFs set at time 350 and clear at the following 350 time. The 
Normal Cycle FFs set at time 00 and clear at the following time 00 providing 
the corresponding Early Cycle FF is set. 

A Master Clear pulse starts the computer in the A cycle. At time A350 the 
Early B or Early C Cycle FF sets, depending upon the condition (ROP) (MUI + 
DVI) + Shift Cycle. At the same time the Early A FF clears. The A Cycle FF 
clears and the B or C Cycle FF sets 50 nsec later. B cycles are followed by 
A cycles either upon a storage resume or (ROP) (IM.OP) condition. C cycles 
are followed by B cycles or another C cycle. The Multiply Step +Divide Step 
condition reinitiates the C cycle. The C Cycle FF does not need a reinitiation 
pulse for Shift instructions. During the shift cycle the Early C Cycle FF does 
not clear because the H06 pulse is not available. Short Cycle 2 (SC 2 blocks 
the setting of H06 and H07 during a shift cycle (see Timing Chain, page 7). The 
(H05) (SC 2 pulse (page 7 module V55) restarts the timing chain after each 
shift, and the computer remains in the C cycle. On the last iteration of shift, 
the SC 2 pulse enables H06, and the Early C Cycle FF clears. 


10 

Rev. A 











ADDRESSING CONTROLS 


The outputs of the four modules below are addressing;<conditions 
used in command timing. These addressing translations enable commands 
used in assembling the effective address. Module V63 contains three 
addressing control FFs. 

READ INDEX 

The setting of the Read Index FF indicates that the present storage 
reference is for the Index register (address OOFF). The Read Index FF 
sets at time A3 00 when the following condition is present: 

ind (i) (RNI + 0) (Wf) 

This condition does not mean that the Indirect and Relative signals are 
unused in forming the effective address. It means that these conditions 
are not available when indexing. Indexing is the last operation in forming 
the effective address. 


The output of the Read Index FF is used in forming other addressing 
conditions. When the set condition is disabled, the Read Index FF clears at 
time A300. 

IMMEDIATE OPERAND (IM. OP^. ) 

The IM. OP. FF sets at time A300 when the indicated condition is 
present. The IM. OP. signal means that the effective address is the operand 
for ReadOperand instructions. The three addressing modes which use IM.OP. 
are marked by an 6 at the bottom of the chart on page 113. The IM.OP. FF 
clears at the first A300 time after addressing is complete. 

A = 0 

The A = 0 FF sets at time A050 of the RNI mode when A = 0. This FF 
enables the P + 1 portion of the effective address and is combined with other 
translations to form addressing conditions. This FF stays set until the next 
A050 time of RNI. 


12 

Rev. AA 



B39 





> 23-C40- 
41 “A45 
t 41 -A46 


;e} 


READ INDEX 


' 23-C40-24'] 

I4I-A4I-9 L (iNT)(ind)(q) 

I 51 -C59-II I (RNI+ A jtOMADR) 
I 51 -D59-2 J 


lind)(q)(RNI + AitO){ADR) + «NT 
39-B40-13 


(INT)(A = 0) 
49>B59-e 


IM. OR (RNIHREAD INDEX) 

I0I-A34-6 

39-A34-6 


IM. OP (r) (READ INDEX) + 


(IM. OR)(ind)(i)(READ INDEX) > END ADR 


(INT)(DISABLE CLR r) 
9-C37-25 


(ind)(ij(RNi + A/OHINT) 
13- B39-20 


lRNi)(r)(A=o)(i4-q)(ind)(iNT) 
STA + STO + S PA R AO -I- RTJ + J M P 
13- B39-8 


NOT 

USED 



(DISABLE CLR r) 
47-B6I -24 




MANUAL CONTROLS (REGISTER SELECTION AND CLEAR CONTROLS) 


A six-position Register Selector switch and associated logic selects 
one of the X, A, Q, P, and Mask registers for manual display and entry. 

The condition (Register Selector switch set) (Display) (T25) sets a 
FF in the V30 module that corresponds to the Register Selector switch 
position. (Since only one position of the Register Selector switch can be 
engaged at one time, two or more registers are not available simultaneously. ) 

The output from the set FF goes to the V41 module enabling an in- 
verter if the condition (Display) (Clear) exists. Then the selected register 
is cleared. The following* table shows the other conditions which cause- a 
register to clear. 


CONDITION 

SPA (STO)(A cycle)(V«50) 

ROP (A cycle) (V250)(MUI) 

(Protec t Fault)(RNI)(A cycle)(Sweep+ 
ENTER)(V05p) 

Interrupt STATE — >Y 

If the Master Clear switch is set, 
taneously. 


CLEARS 

entire A register 
entire Q register 

upper 8 bits of X register 
upper 8 bits of Y register 

all six registers clear simul- 


14 

Rev. A 



063 


C36 



31- C45-I3 
31- C46- 13 


} 


33-049 

33-048 




UPPER 8 BITS 
39-B46- 


6- 13 'I 

7- 13 J 


UPPER 8 BITS 
41- A47-I3 ' 




37- A44- 13 
I9-A63-27 


67- 041-28 1 
67- 042-28 I 
67- 043-28 I 
71- 044-28 I 


CLEAR A 


CLEAR Q 


CLEAR X 


CLEAR Y 


CLEAR P 


CLEAR MASK 


NOTES : 

I. CAPACITOR VALUES ON V30 MODULE MAY BE 0.1 fiF ON 
SOME MACHINES. SEE CHANGE ORDER NO. 14392. 




CONTROL DATA 
CORPORATION 


T«TL« 

PHODUCT 


MANUAL CONTROLS 

1704 


(REGISTER SELECTION AND 

• IZI 

c 

60152700 

NCV 


COMPUTER DIVISION 


IfIT 


15 


MANUAL CONTROLS (SWITCH AND INDICATOR DRIVERS) 


The Selective Skip, Program Protect, and Enter/Sweep switches 
connect to the V66 module. The Selective Skip switch is a 3-posi- 
tion lever switch that is OFF in the center position; ON in the up 
and down position. The up position is fixed and the down position 
is momentary. The Selective Skip switch in the ON position con- 
ditions the Selective Skip instruction shown on page 43. Placing 
the Program Protect switch in the up position, conditions the 
Program Protect logic shown on page 69. 

The Enter/Sweep switch is a 3-position lever switch which is 
fixed in all positions with the center position OFF. In the 
ENTER position, each step operation of the Run/ Stop switch 
stores the contents of the X register at the location specified by 
the P register and advances the P register by one. In the SWEEP 
position, each step operation of the Run/Stop switch transfers the 
contents of the storage location whose address is in the P register 
into the X register and advances the P register by one. 


The 16 pushbuttons connected to the V66 and V67 modules control 
manual entry into a selected register. A set pushbutton ANDed 
with the Display condition sends a "O" to the Adder/Shifter. This 
puts a "l" into the corresponding bit position of the selected register. 
The indicators on the two V68 modules (locations A 64 and B64) dis- 
play the contents of the selected register (Display condition present). 
An enabled indicator represents "l" in that location. 

When set, the Clear pushbutton attached to the V66 module clears 
the contents of the selected register. When a bit is manually set, 
it remains in that state until the Clear pushbutton is enabled. 

A V68 module (location C64) controls the eight indicators (excluding 
TEMP) located on the left side of the 1700 console. Note that a "0" 
input enables the corresponding indicator. 



+ 6V 


E64 

fviil 


C64 

| V68 

27 . 




PROGRAM 

PROTECT 

FAULT 


STORAGE 

PARITY 


OVERFLOW 

PROGRAM 

PROTECT 

INSTRUCTION 


OPERAND 


INDIRECT 

ADDRESS 


STORAGE 

INDEX 


A64 


B64 




NOTES : 

I. CAPACITOR VALUES ON V66 AND V67 MODULES MAY 
BE 0.1 ON SOME MACHINES. SEE CHANGE ORDER 
NO. 14392. 





CONTROL DATA 
CORPORATION 


MANUAL CONTROLS 
(SWITCH 8k INDICATOR DRIVERS) 


I MtODUCT 

1 1704 


I flit loBAwiat ao. 

C 60152700 


Umcct I n 

J 12 


17 


COMPUTER DIVISION 



MANUAL CONTROLS (TEST MODE AND RUN/STEP) 


The Test Mode switch connects to module V85. Modules V85 and 
V88 contain the Test Mode logic. The computer executes the following 
sequence of events when the Test Mode switch is placed in the down 
position: 

1) 20 usee Master Clear. This clears the P register and all 
other operational registers, 

2) 100 usee program run starting from P = 0000. 

3) Return to step 1 and repeat. 

The accompanying timing chart shows the setting and clearing of 
the three Test Mode FFs. The Test Mode Go FF enables a 100 usee Go 
pulse to the Gol FF on module V49. The Gol FF sets the Go2 FF 75 nsec 
later. The Go2 pulse starts the timing chain which runs for 100 usee or 
until a program Stop is enabled. At the end of 100 usee the Test Mode 
Clear FF enables the Master Clear and the timing chain stops. 


TEST MODE CLEAR 


TEST MODE 60 


r 


ENABLE 
TEST MODE 
SWITCH 


CLEAR STOP 1 
^ AND MC 

20£SEC 

rn 100 USEC 



clear stop I 
^ and mc 

20 USEC 


JL_ 


SET GO 2 


A 



MASTER CLEAR (MC) 

The Master Clear switch connects to module V85. A Master Clear 
is executed when the switch is momentarily placed in the up or down posi- 
tion. The Master Clear disables the timing chain, clears all registers, and 
clears most Control FFs. Modules V85 and V06 contain Master Clear 
fan-outs. 

Module V88 contains a delayed Master Clear for storage control. 
This allows the completion of the present storage reference and prevents 
unnecessary fault conditions from occurring. 

LOGIC VOLTAGE SENSOR 

Module WOO is used to determine power failures by sensing the 
+6-volt logic bus. When the voltage drops below a preset value, the 
special circuit de-energizes relay K4 arid protects memory. AhotheV 
output of module WOO is used to generate interrupt 00 on power failure. 
Approximately 8 milliseconds of program execution time is available 
between relay coil de- energization and contact closure. 

The logic voltage sensor can be disabled for voltage margin checking 
by turning the MARGIN MODE switch on (this switch is located on the 
memory power supply). 


18 

Rev. F 



SLS(RE6)(B CYCLE) 
5I-C59-I0 


.23 


A63 



2. CAPACITOR VALUES ON V49.V66 AND VSS MODULES MAY BE 0.1 /iF ON 
SOME MACHINES. SEE CHANGE ORDER NO. 14392. 


€- 


CONTROL DATA 
CORPORATION 


TITLI 

rROOMCT 


MANUAL CONTROLS 

1704 


• HI 

HO. 

[T7r 

(TEST MODE AND RUN /STEP) 

c 

60152700 

Ll 


COMPUTER DIVISION 


HIT 


19 




TYPICAL REGISTER DISPLAY 


The diagram below shows a typical register display sequence using the A register. 
For a starting reference, assume the following conditions: 

1) Power on 

2) A register selector button pressed 

3) Timing chain stopped 

4) Display FF set (enabling pushbuttons and display) 


When the Run/ Step switch is momentarily placed in the up position (RUN), 

the timing chain starts and the switches and display are disabled. The following 

timing chart shows the setting and clearing of Control FFs for starting the 


computer. 


COMPUTER STOPPED- 
ENABLE RUN SWITCH 


STOP I CLEAR 
STOP n: 

NEUTRAL 

RUN 

GO I 

GO H 

DISPLAY 
REG SEL 
A— > ADDER 
ADDER — ►A 


00 00 00 


I 

I 

I 


I 

L CLEARS AND 

ENABLES RESTART 

— i^J. 

,.i RESETS WHEN SWITCH 
“jJJ RETURNS TO NEUTRAL 
I 
I 


I 

I 


^ START TIMING CHAIN 

1 ^ 

I 

BLOCKS DISPLAY AND SWITCHES 

i 


^ BLOCKS MANUAL SETTING 
I OF A REGISTER 


The timing chain is disabled and the display enabled when the Stop FFs set. The 
timing chain can not be restarted until the Run/ Step switch is activated. The 


individual bits of the A registers are manually set by the bit pushbuttons while the 
Display FF is set. Pressing a bit pushbutton enables the Adder/Shifter to set the 
corresponding bit in the A register and light the corresponding bit indicator. 

The raw clock pulses enable the setting of the A register, although the timing 
chain is stopped. The following timing chart shows the setting of Control FFs 
for stopping the computer. 


00 00 

COMPUTER RUNNING- I t i i I 
ENABLE STOP T 


SET 

CLEAR 


■ii- 


STOP I 

STOP n 

NEUTRAL 
RUN 
GO I 
GO U 
DISPLAY 
REG SEL 
A— >ADDER 
ADDER — >A 


TIME 

025 


-Ji- 


-iS- 

-iS- 

-ii- 

■iS- 

rff 

-!!■ 

^S- 

if 


00 00 00 


I I 


I 

I 


I 

I 

REMAIMS SETS 

I 


RESUME 


REMAINS CLEAR 


REMAINS CLEAR 
I 

REMAINS CLEAR 

I 

I 

I 


I 

I 


I 

I 


A REGISTER 


SETS AT too AFTER ADDER— » A SETS 
WHEN BIT PUSHBUTTON IS ENABLED 


Pressing the Clear pushbutton clears the A register if the Display FF is set. 
Other registers may be selected while the Display FF is set by pressing the 
corresponding register selector switch. For example, if the X register is 
selected, the Adder/Shifter samples the X register and the corresponding bit 
indicators light. 

20 . 1 

Rev. R 



TYPICAL REGISTER DISPLAY (Cont’d) 


The computer is stopped momentarily by placing the Run/ Step switch in the 
down position. If the switch is repeatedly placed in the down position, 
the computer steps through the program, stopping after each storage ref- 
erence, The significance of the storage reference just made is indicated by 
the instruction sequence indicators. 

This diagram shows a typical register display sequence (A register). The register 
selector switch must be set for the A register. With the Run-Step switch (page 19) 


in the center position, the Neutral FF is set. When the switch is placed in the 
STEP position, the timing chain stops at the end of the current storage refer- 
ence and the display is enabled. During the step sequence, the Go 2 FF remains 
cleared and the Stop 2 FF sets, thus disabling the timing chain at the end of 
the B cycle. The Display FF sets when Stop 2 is set and a Resume and 75 time 
are present. Each step pulse sets Go 1, Go 2, and moves the timing chain one 
storage reference. The chain is stopped by the 125 pulse clearing Go 2 before 
the next storage reference. 


20. 2 
Rev. R 






CONTROL DATA 
CORPORATION 


^MODUCT 


1704 


MANUAL CONTROLS 
(TYPICAL REGISTER DISPLAY) 


rtiir 




C 1^152700 


COMPUTER DIVISION 


l«T 



F REGISTER 


The 8-stage F register is divided into two 4-stage groups contained on two 
V57 modules. The low-order four stages (F8-F11) contain the instruction 
designator bits. The high-order four stages (F12-F15) contain the f instruction 
designator bits. The stages of the F register are numbered 8-15 to coincide with 
the instruction bit positions that they contain. The outputs of the F register 
translate into the various function codes. 

In storage reference instructions, the low- order stages of the F register contain 
the relative (r), indirect (ind), Q register index (q), and storage index (i) 
designators as shown on the diagram. In this type of instruction, the designators 
control the addressing mode of instruction execution. 

X - F CONTROL 

At t25 time of each RNI sequence, inverter A forces a "O" input to B on the V57 
modules. The outputs of A and B transfer the high-order eight bits in X to F. 
Thus, the f and f^ designator portions of the instruction are transferred at this 
time. 

F REGISTER CLEAR CONTROL 

The diagram shows the conditions under which both the f and f^ positions are 
cleared. The enabling of one of these conditions, e.g.. Protect Fault, produces 
"0" outputs from inverters E and F on the V56 module. The resulting "1" 
outputs from the output inverters on this module clear the F register. 

During the ADR mode of storage reference instructions, the r, ind, q, and i 
designators in the fl portion are cleared individually. The following table 


lists the conditions for clearing each of the designators. 


Designator Conditions Time 


r (Fll) (ADR) (B cycle) ( Disa bl e Cl r r) V300 

ind (FIO) (ADR) (A cycle) (X15) (RNI) (Fll) VlOO 

q (F9) (ADR) (INT) (ind) (q) (RNI + A 0) (B cycle) VlOO 

i (F8) (Read Index) (B cycle) V300 


Timing pulse V300 clears the r designator during the B cycle of the ADR mode 
if condition (Disable Clr r) is present. At this time, all relative addressing is 
complete. If r was not initially set, the operation becomes irrelevant. 

The above table shows that the clearing of ind dur in g th e A cycle of ADR 
following the reading of the indirect address (RNI) (Fll) depends on the state of 
bit 15 contained in the X register. If this bit is a ”l" indicating that the address 
corresponds to another indirect address, VlOO does not clear ind. If this bit is 
a "0", indirect addressing is complete and ind is cleared. 

The VlOO pulse clears q during the ADR mode on a INT condition. If indirect 
or relative or both Addressing modes were initially specified, these operations 
are completed first. The condition for clearing q specifies that q must be 
initially set. 

The V300 pulse clears i during the B cycle on a Read Index operation. The 
condition for clearing i need not specify the ADR mode since a Read Index can 
occur only during this mode. The adding of the i index always takes place last 
if any other addressing mode designators were initially set. 


22 

Rev. AA 




> I3-B39-24 FJl 



25-B5I-8 
25 -A50-9 
13 -057-9 
NU 


25-B5I-7 
25 -A50-8 
13-057-21 
13-025-12 


25 - A5J-I6 
25 -A50-I5 
13 -057-25 
25-B5I-27 


.CONTROL DATA 
CORPORATION 


1704 


F REGISTER 


60152700 


COMPUTER DIVISION 



FUNCTION TRANSLATORS 


The Function Translators translate the contents of the F register 
to obtain the current instruction. The 1700 repertoire of instructions 
may be grouped into Storage Reference instructions (F portion) and Reg- 
ister Reference instructions (F"^ portion). In the table of instructions on 
page 26, the Storage Reference instructions are in column one (beginning 
with JMP) and the Register Reference instructions are in column three 
(beginning with SLS). 

Register Reference instructions are identified when the upper 4 
bits (15-12) of the instruction are all "O's". The format of Register 
Reference is diagrammed below: 


15 12 II 8 7 0 



INSTRUCTION MODIFIER (A) 


Storage Reference instructions have their instruction code in bits 
15- 12, and bits 11-08 become the address mode. Storage Reference 
instruction format is diagrammed below: 


15 12 II 8 7 0 



INSTRUCTION DELTA (A) 


The static logic of the Function Translator translates the 16-bit 
input to the selected instruction. The logic searches through the input 
until it recognizes a unique instruction. The Function Translator 
dispenses the signals that enable the selected instruction and its associated 
logic. 


24 

Rev. AA 






17 


, IR 

'25-B51-20 


REG (IR) 
5I-D59-3 



FUNCTION TRANSLATIONS 


REGISTER REFERENCE 


INTER-REGISTER 


JMP 

JtDEp 

0 

0000 

SLS 

Selective Stop 

MJI 

Multiply 

1 

0001 


SKIPS 

DVI 

Divide 

2 

0010 

INP 

Input to A 

STQ 

Store Q 

3 

0011 

OUT 

Output from A 

KTJ 

Ret. Jmq} 

4 

0100 

EIN 

Enable Int. 

STA 

Store A 

5 

0101 

IIN 

Inhibit Int. 

SPA 

STA, Parity A 

6 

0110 

SPB 

Set Prgm. Pro. 

ADD 

Add to A 

7 

0111 

CPB 

Clr. Prgm. Pro, 

SUB 

Sub. from A 

8 

1000 


I RTS 

AND 

AND with A 

9 

1001 

INA 

Increase A 

EOR 

Exc. OR/A 

A 

1010 

ENA 

Enter A 

LDA 

Load A 

B 

1011 


NO-OP 

RAQ 

Replace Add 1 

C 

1100 

ENQ 

Enter Q 

LDQ 

Load Q 

D 

1101 

INQ 

Increase Q 

ADQ 

Add to Q 

E 

1110 

EXI 

Exit Int. 



F 

1111 


Shifts 


76 5 452 >0 

[ooooli oool I |a|q|mIa]o|m| 


LOGICAL PROD - ■ » 

EXCLUSIVE OR — ' 

ORIGIN REGISTERS 

DESTINATION REGISTERS - 


ORIGIN REGISTERS 

If A(B+5)=0; OPl = FFFF 
If Bits 3+4 = 0; 0P2 = FFFF 
If Bits 3+4 = 1; 0P2 = (Q)+(M) 

LP+XR 

Both =0; Sum of OPl + 0P2 
Both = 1; Coenplement of LP 


0 0000 SAZ A = +0 

1 0001 SAN A ^ +0 

2 0010 SAP A = + 

3 0011 SAM A = - 

4 0100 SQZ Q = +0 

5 0101 SQN Q ^ -0 

6 0110 SQP Q = + 

7 0111 SQM Q = - 

8 1000 SWS Skip SW. 

9 1001 SWN Skip SW. 

A 1010 SOV Overflow 
B 1011 SNO Overflow 

C 1100 SPE Parity Error 
D 1101 SNP Parity Error 
E 1110 SPP Prgm. Pro. Fault 
F 1111 SNP Pr^. Pro. Fault 


LEFT 

SHIFT A 

SHIFT Q 

SHIFT COUNT 


26 

Rev AP 





D5I 

IV79l 



(SUB -f MUI+DVI) ROP 
39-B40-I6 

sUb 

29-A57-5 

(ADO SUB f RAO f ADO) ROP 
57-036-3 

(ADD -I- SUB + AND 4 EOR) ROP 
29-A57-9 


(ADO +SUB + AND + EOR + MUI + DVI) ROP 
49-A59-2 


(ADD 4 SUB + AND4E0R4LDA)(R0P)(RNI) 
3I-C4I-28 


RAO (ROP) 
I0J-A34-I4 

RAO 

29-C5I-25 


49-B59-J0 
5I-C59 -9 


} 


(ADO) ROP 


MUI 4 0VI4 ADO (ROPI) 
5I-C59-24 


LDQ4 ADO 
33-D39-2 


49-B59-20 
51 - D59- 14 


} 


(MUI+ 0V14EXI) ROP 


JMP 4STQ 4 RTJ 4 STA + SPA4 RAQ 
I3-D57-26 




CONTROL DATA 
CORPORATION 


TITLl 

FUNCTION TRANSLATIONS 


^Moouer 

1704 

•izc IsiAwma . 

C 60152700 I 


COMPUTER DIVISION 


<CET 







FI2 

23-B48-22I 


16 


C5I 



j|L CONTROL DATA 

TITtl 

CORPORATION 



FUNCTION TRANSLATIONS 


1704 

‘cTeoi'seToo 


COMPUTER DIVISION 


ItNCCT I MtE 



A REGISTER 


The 16- stage A register functions as the Main Arithmetic register. The main 
functions of the A register are: 

1) To contain one operand during many Arithmetic and Logical operations, 
such as ADD, SUB, AND, etc, 

2) To provide a means of loading operands into the arithmetic section (LDA) 
and of storing the results of Arithmetic or Logical operations in storage 
(STA, SPA). 

3) during multiplication operations, to initially contain the multiplier. At 
the completion of the multiply, the A register contains the low-order 
16 bits of the 32-bit product. 

4) during divide operations, to initially contain the low-order 16 bits of the 
dividend, and at the completion of the divide, to contain the quotient. 

5) in input or output operations, to contain the input or output data respectively. 

The A reigster is divided into two 8- stage portions contained on two VOl modules. 
The outputs of the A register transfer to the Adder/ Shifter through the A fan-out 
modules. The A register receives inputs from the Adder /Shifter fan-out, the 
input receiver modules in the A/Q interface, or the receiver modules in the 
low- speed interface through the A register fan-in modules. The input selection 
is controlled by the Adder-* A and Input -*A FFs on the V40 module. 


ADDER -* A 

The Adder -►A FF selects the Adder/ Shifter input to the A register. The 
diagram shows that this FF is set at one of three V-50 timing periods by the 
enabling of the corresponding conditions. The setting of the Adder -* A FF 
forces a "O" input to inverters A and B on the VI 5 and to inverter A on the VI 6 
fan-in modules. The "l" outputs of these inverters enable the Adder /Shifter 
outputs to the corresponding inverters on the VI 5 and VI 6 modules. The 
following too pulse gates the outputs of the fan-in modules into the A register. 
Thus, the Adder -*A FF is set on the tSO time preceeding the tOO pulse that 
loads the A register, allowing 50 nsec for the inputs to stabilize. The t25 
pulse always clears the Adder -*A FF, The A -* Adder pulse also sets the 
Adder -► A FF on a manual selection of the A register. 

The A register receives an input from the Adder/ Shifter in four main types 
of instruction operations. Each of the four types is given below with a brief 
description of the conditions for each type. 


Shift 

In (A) Shift instructions, the Adder — A FF is set at two unique times. The 
V050 pulse sets Adder -*A in each C cycle with the A -* Adder enable through 
inverter F. The V250 pulse also sets Adder -* A in the C cycle under the 
same conditions. Thus, Adder -*A is set twice (A shifted twice) during each 
C cycle if Y (shift count) is not found to be "O” before each shift. 


During short cycle (SCI) operations in Multiply and Shift instructions, the 
V250 pulse occurs 100 nsec earlier, corresponding to the short cycle of 
the operand transmission through the adder/ shifter. 

In (AQ) shifts, Adder - A is set only at V250 time since the A - Adder 
signal is not present at the V050 time. 

Multiply Divide 

In Multiply or Divide operations, Adder A is set during the B and C cycles 
in the ROP mode. The setting of Adder -► A on the B cycle at 250 time 
transfers the complemented A (A initially negative) or the uncomplimented 
A (A initially positive) back to the A register. In Multiply operations, the 
V150 pulse sets Adder -*■ A which transfers the low-order bits of the final 
product to the A register. In Divide Step operations, the setting of Adder A 
at this time transfers the shifted partial dividend back to the A register. 

IR + ENA + INA 

The Adder - A FF is set on V250 time of the A cycle in the REG mode in 
the Enter A (ENA) and Increase A (INA) instructions. In either of these 
instructions, the new quantity is transferred to A at this time. In IR 
instructions, the setting of X2 selects the A register as the destination register. 
In this case, the V250 pulse sets the Adder -* A FF in the A cycle. 

LDA + ADD + AND + EOR + SUB 

In these instructions, the V250 pulse sets Adder — A during the B cycle which 
enables the transfer of the arithmetic or logical result to the A register. 

SPA 

The V250 pulse sets Adder A in the SPA instruction during the A cycle of 
the STO mode if the parity bit of the word being written in storage is a ”1'' 
(parity even). The setting of Adder - A at this time enables the transfer of a 
+ 1 to the A register. 

INPUT - A 

The Input A FF enables the transfer of the output of the input receivers in the 
A/Q or low- speed inte rface to the A r egister through the fan-in modules. The 
setting of Input A in Character mode forces "1" outputs frpm the output 
inverters C and D on the VI 5 modules and inverter B on the VI 6 modules. The 
outputs of these inverters enable the selected input receivers to the fan-in 
modules. The tOO pulse transfers the 16-bit data word to the A register. 

In the Character mode, the "0" input to the * inverter disables the input transfer 
to the high- order eight stages of the A register. The 8-bit character transfers 
to the low- order eight stages of the A register at tOO. 

The V250 pulse sets the Input A FF during the A cycle of the INP instruction 
if the selected input device sends no Reject signal. 


30 

Rev. A 









Q REGISTER 


The 16 -bit Q register (auxiliary arithmetic) assists the A register in performing 
arithmetic and logical operations. The Q register is also used as an Index register 
for storage reference instructions and as an Output Address register for non- 
buffered I/O. 

The Q register is divided into two VOl modules and receives its inputs from four 
V06 Adder/Shifter fan-out modules. The outputs of the Q register return to the 
Adder/ Shifter via the A, Q fan-out modules. and addend gates. 

The Adder -*Q FF controls the input to Q register selection. 


ADDER CONTROL 

The Adder -*-Q FF’has three main setting gates. The first is satisfied if the manual 
Q register selector on the console is activated and the O Adder FF is set. 

At time V050 of the C cycle, the second gate is enabled if one of the indicated 


conditions is satisfied. At time V250, the third gate is enabled if one 
of the indicated conditions is satisfied. The t25 pulse clears the Adder 
Q FF in all cases. 

The setting of the Adder —Q FF enables a pulse to the A and C inverters of 
the VOl modules at tOO. Therefore, the transfer from the Adder/Shifter to the 
Q register occurs 50 nanoseconds after the Adder -♦Q FF is set. 


If the condition HOI (Div. Step)(EAB) is not satisfied, inverter* has a '*1" 
output and the transfer of data to the Q register is blocked, even though the 
Adder -*Q FF is set. This condition may occur during a divide step when 
subtracting (X) from (Q). An EAB occurs when X > Q. 

The Q register clears when either the manual clear or Master Clear is selected. 
The inverters on V41 send a pulse to inverters E and F on the two VOl modules, 
clearing all Q register FFs, 


32 

Rev. A 



ADDER SI 



ADDER S 


Q REGISTER (UPPER 8 BITS) 



»«OOUCT 

1704 


C 6015 2700 


COMPUTER DIVISION 



A, Q FAN-OUT 


The A, Q FANOUT provides three additional outputs for the A and 
Q register. 

The Adder/Shifter Fan-In, AQ I/O, and Skip FF receive the contents 
of the A, Q FANOUT, The inverters in each Module send several bits in 


a group to the Skip FF. If the group of bits in "0", the output of 
inverter is a "0", which is inverted and sent to the Skip FF. T 
Skip FF searches for Zero contents of the A or Q registers. 




A . Q FANOUT 


60152700 






P REGISTER 


The P register contains the address of the current instruction. In most cases, 
the P register advances by one near the completion of each instruction. The 
outputs of the P register enter the addend gates of the Adder/ Shifter. The 
Adder/Shifter forms the next instruction address, returning it to the P register. 

The P register consists of 15 stages divided into two VOl modules. The P 
register receives inputs from four V06 Adder/Shifterfan-out modules. The 
V06 modules provide the input gates which select the Adder/Shifter inputs. 

The Adder *^P FF controls the input to P register selection. 

ADDER -P CONTROL 

The Adder -*P FF has three main setting gates. The first gate is satisfied 
if the manual P register selector on the console is activated and the P Adder 


FF is set. At time V050 of the B cycle, the second gate is enabled if 
one of the indicated conditions is satisfied. At time V250, the third gate 
is enabled if one of the indicated conditions is satisfied. The t25 pulse 
clears the Adder -*P FF in all cases. 

The setting of the Adder -*P FF enables a pulse to the A and C inverters 
of the VOl modules^at tOOCif I Therefore, the transfer from the Adder/ Shifter 
to the P register occurs 50 nanoseconds after the Adder -►P FF is set. 

The P register clears when either the manual clear or Master Clear is 
selected. The inverters on V41 send a pulse to inverters E and F on the 
two VOl modules, clearing all P register FFs. 


36 

Rev. A 



P REGISTER (UPPER 7 BITS) 






X REGISTER 


The X register consists of 16 stages divided into two VOl modules. The X register 
receives inputs from the Z register and the Adder/Shifter through the two VI 9 fan-in 
modules. The VI 9 modules provide the input gates which select the Z register or 
Adder/ Shifter inputs. 

The Resume and Adder ^ X FFs control the input to X register selection. The Resume 
and Adder ^X control FFs are described below. 


Z - X CONTROL (RESUME) 

The Storage Resume signal sets the Resume FF at time t50 and clears the Req. Mem. FF 
This time is relative to 50 nsec before the Resume transfer actually takes place. A 
Storage Write operation causes F to block the Resume output of V82. Thus the Resume 
transfer occurs only on Storage Read operations. 

The outputs pass through inverters G and H and apply "l" inputs to A and C in the 
VOl modules. Additional Resume outputs enter C and D in the fan-in (V19)modules. 

As a result, the Z register "l" bits enter the X register at time tOO. The X 
register stages corresponding to ”0's" are cleared. 

The t25 pulse clears the Resume FF. Thus, this FF remains enabled for 75 nsec 
after it is set. 


ADDER - X CONTROL 

The Adder -^X FF has four main setting gates. The first of these sets the 
Adder -X FF during a B cycle at time V050 if one of the indicated conditions is 
satisfied. The remaining three main gates set the Adder -►X FF at time V250 
if the necessary conditions are satisfied. The X Adder enable also sets the FF 
in a manual selection. The t25 pulse clears the Adder -►X FF in all cases. 

The setting of the Adder X FF enables the Adder/Shifter input to the X register 
through inverters A and B on each VI 9 module. Thus, the tOO pulse transfers 
the Adder/ Shifter output to the X register. 


X REGISTER FAN-OUT 

The X register output passes through four fan-out modules to obtain additional 
outputs and for control functions such as the extending of the A sign bit. 

The low- order five stages of the X register pass through the V26 module. 

Each of the low- order four of these stages has four outputs that go to destinations 
indicated, (Stage 04 has one additional output to the translator. ) The A == 0 
translation is also sensed on this module for the low- order five stages - 

Stages 5, 6, and 7 pass through the V2 7 module. These stages each have six 
outputs as indicated. 

The high- order eight stages of the X register pass through two V28 modules. 
These stages have four outputs as shown except the sign bit (stage 15) and stage 
1.1, The extra outputs of stage 11 are not used. The V28 modules also sense 
for the F 0 condition of the corresponding bits. 

SKIP TRANSFERS 

In the execution of a Skip instruction, the low- order four bits of the instruction, 
and thus the X register, contain the skip count. The outputs from stages 
04-07 at this time are "O's". Thus a REG operation during a Skip instruction for- 
ces "0"outputs of stages 04-07 to the Addend gates and the Augend gates. 

EXTEND SIGN 

In the type of operations indicated, the sign bit of A (stage 07) is extended in 
the high- order eight outputs. If one of the indicated conditions is enabled and 
bit 07 is a "1" (negative sign), the output of the sign extension inverters on the 
V27 module enter inverters A and B on the two V28 modules. The outputs of 
A and B force "0" inputs to the fan-out inverters that feed the Addend and Augend 
gates. Thus, the high-order eight outputs to these gates are all "I's". 

If, in a sign extension operation stage 07 contains a "0" (positive) , inverter A 
on the V2 7 module forces "0" outputs from the sign extension inverters. The 
resulting outputs of A and B on the V28 modules gate the outputs of the high- 
order eight stages of the X register, which are cleared, at V050 time of each 
RNI sequence to the augend and addend gates. 


38 

Rev. A 













Y REGISTER 


The 16-bit Y register is contained on two VOl modules. The Y register contains 
storage addresses for subsequent transfer during a storage reference. The Y 
register is also used as a counter during Multiply, Divide, and Shift instructions. 

The first VOl module contains bits 00-06 and bit 08. The second VOl module 
contains bit 07 and bits 09-15. Bits 00-05 and bit 08 receive inputs from a 
V22 module, and bit 06 receives its input from a V42 module. The second VOl 
module receives its inputs from the V06 Adder /Shifterfan-out modules. 

The control. FFs for the Y register are contained on the V42 module and receive 
set inputs from the V43 module. The Y register outputs feed VI 3 and V14 fan- 
out modules and are gated to the S register, Adder/Shifter or Y decrementer. 

All control FFs set at t50 and clear at t25. The Y register gating occurs at 
too. Therefore, the actual transfer to the Y register occurs 50 nsec after the 
control FFs are set. 

The Y register clears when either the manual clear or Master Clear is selected. 
The clear pulse enters inverters E and F on the two VOl modules, clearing all 
Y register FFs. 


ADDER - Y CONTROL 

The Adder -► Y FF has three main setting gates. The first gate is satisfied if 
the manual Y register selector on the console is activated and Y Adder FF is 
set. At time V050 (V42) of the B cycle (V43), the second gate is set if one of the 
indicated conditions is satisfied. The third gate is set at time V250 (V42) of the 
A cycle (V43) if one of the indicated conditions is satisfied. The setting of the 
Adder -► Y FF enables inverters A and B on the V22 module and A and C on the 
second VOl module. The V22 module provides the Adder/ Shifter input gates for 
selecting bits 00-05 and bit 08 of the Y register. Module V42 provides the input 
selection for bit 06. The second VOl module receives its inputs from the V06 
Adder /.Shifter fan-out modules. 

For Shift instructions, the Adder Y FF enables the lower 8 bits of the shift 
instruction format into the Y register. Bits 00-04 contain the shift count. 

For other instructions, the Adder Y FF enables the effective address or 
partially modified address into the Y register. The effective address is held 
in the Y register until transfer to the S register during a storage reference. 

Bit 15 does not transfer to the S register. Bit 15 is a sign bit when the 
effective address is an operand for Read Operand instructions. 


DECREMENT Y CONTROL 

The Decrement Y FF has three main setting gates. If any one of the following 
gates are satisfied, the Decrement Y FF sets and the value in the lower 5 bits 
of the Y register decreases by one. 


Time (V42) 

Cycle (V43) 

Condition 

V050 

C 

(YOO-04 0) (REG)(SHIFT)(QA SHIFT) 

V250 

C 

(YOO-04 f 0) 

V250 

or* 

A 

(YOO-04 i 0) (ROP) (MUI) 

V350 

A 

(YOO-04 4 0) (REG)(SHIFT) 


The Decrement Y FF enables the C inverter on the V22 module, and the A 
and C inverters on the first VOl module. This gates the decremented value 
of Y back into the lower 5 bits of the Y register to tOO. Five bits are used 
to express the maximum shift count of - 37g = Five bits are also 

needed for the multiply and divide when tne Y register decrements from 

10i6 (20g = 16jo> too. 


V2£ VOl V13 V08 



In short cycle (SCI) operations which occur only in shift or MUI instructions, 
the V250 pulse occurs 100 nsec earlier. This case effects only condition 2 
listed previously. In this condition, the Decrement Y FF’ is set 100 nsec earlier 
since the short cycle requires 100 nsec to transmit the ope rand 'through the 
Adder /Shifter. 


lO^g -Y CONTROL 

The 10., o Y FF establishes the starting Y register count (10. „) for Multiply 
and Divme instructions. As each shift and compare sequence^ ^is done, the 
Y register decrements by one until YOO-04 = 0. 

The 10. g - Y FF sets at time V050 (V42) of the A cycle (V43) when ROP and 
MUI + DVI signals are present. The 10. — Y FF enables bit 04 of the Y 

register to set at time 00, thus forming a ^ ^binary 10000 (lO^^g). 


STATE - Y CONTROL 

The State -► Y FF enables the forming of an address to locate the return 
addresses for each of the 16 possible interrupt states. The table on page 
71 shows the interrupt states and location of return addresses. The location 
of the return addresses may be formed by changing bits 02, 03, 04, and 05 
and setting bit 08 to a "1". 


Y REGISTER 


}5 

0 0 0 0 I 0 

I 

0 

0 

0 

0 


08 07 06 05 04 03 02 01 00 

00 i|oo--|--oo| 

I i i 

I 0 0,4,8,c 

I I 0,4,8,C 

I 2 0,4,8,C 

I 3 0, 4,8,C 


The State - Y FF sets at time V050 (V42) of the B cycle (V43) when an 
Interrupt signal is present. The State Y FF enables inverter D on the 
V22 module and inverters A and C on the first VOl module. Four interrupt 


40.1 
Rev. A 






Y REGISTER (Cont'd) 


state inputs are gated into the V22 module from the VI 1 and V12 module on 
page 71. At tOO, the state inputs are gated into bits 02, 03, 04, and 05 of 
the Y register and bit 08 is set to a "1". The address to locate the return 
address transfers through the VI 3 and VI 4 modules to the S register. 


CONSOLE INDICATOR CONTROL 

Module V43 contains the control for three console indicators. The three 
indicator outputs are enabled by a display pulse on module V55, page 21. 
The display pulse enables the indicators only if the following conditions 
are present: 


1) Indirect Address = (IM. OP. ) (READ INDEX) ADR 

2) Storage Index = READ INDEX 

3) Operand = STO + ROP + IM. OP. 

(IM.OP. (ROP) CONTROL 

An inverter whose output is (IM. OP, ) (ROP) is located on the bottom of module 
V43. This pulse feeds module V55, page 7, and is one of the conditions which 
stops the timing chain. 


40.2 
Rev. A 











Y-DECREMENTER 


The Y-Decrementer operates as a counter during Multiply, Divide, and Shift 
instructions. The lower 5 bits of the Y register hold the shift count which 
decreases by one on each pass through the decrementer. The decrenaenting is 
performed logically by inspecting each bit in order, starting with YOO. Each bit 
is complemented until the decrementer reaches a ”l". The ”1" is complemented 
and the remaining higher bits (if any) are transferred through the decrementer 
without being changed. For example, if YOO is a "1" it is complemented, but 
YOl-04 remain unchanged during this particular pass. 

When the count is reduced to zero (Y00-04=0), the gate in the lower-right corner 
of the VOS module is enabled, the Y-Decrementer is disabled, and the shifting in 
the current instruction is completed. 

SKIP FF 

A zero is the instruction field and a one in the sub-instruction field 
identifies a Skip instruction. Diagrammed below is the Skip instruction format. 


15 12 II 8 7 4 3 0 



SUB- INSTRUCTION 
(F I ) 


When the skip condition is met, the contents of the skip count +1 is 
added to P to obtain the address of the next instruction (e.g. , when the 
skip count is zero, go to P + 1). When the skip condition is not met, the 
address of the next instruction is P + 1 (skip count ignored). The skip 
count does not have a sign bit. 


The Z81 and V53 modules examine X04-07 to determine which skip 
instruction is to be executed. The table following illustrates the possible skip 
instruction translations and their conditions. 

The Skip instruction conditions (contents of A and Q registers. 
Selective Skip switch. Overflow, Storage Parity Error, and Program Protect 
Fault) enter the Z81 module. The contents of the A and Q registers are 
sensed for sign and for zero or not zero. 


Skip Instruction 

Bits 

Skip If 

(Hex. ) 

7|6|5l4- 


0 

0000 

A = +0 

1 

0001 

A ^ +0 

2 

0010 

A = + 

3 

0011 

A = - 

4 

0100 

Q = +0 

5 

0101 

Q +0 

6 

0110 

Q = + 

7 

0111 

Q = ” 

8 

1000 

Switch set 

9 

1001 

Switch not set 

A 

1010 

Overflow 

B 

1011 

No overflow 

C 

1100 

Storage Parity Error 

D 

1101 

No Storage Parity Error 

E 

1110 

Program Protect Fault 

F 

nil 

No Program Protect Fault 

i 


The logic in the Z81 and V53 modules recognizes the selected Skip 
instruction and determines if its conditions are satisfied. The conditions 
(VI 50) (REG) (SKIP) and the Skip instruction satisfied enable the Skip FF. 

The setting of the Skip FF sends a "l" through two inverters to the Adder 
P FF shown on page 37. 

The condition (REG) (INP +OUT) (Reject) sends a "1" through two 
inverters to the same Adder -> P FF as the Skip FF. 

The condition (INP) (REG) (Reject) sets the I/O— A FF shown on page 31. 


-42 

Rev. A 





41- A49-22 


141- A49-I7 


AOS, 10-13, ISsO 35-C42 -23' 
A06-09*0 35-C43-6 ' 
A00-04,t4*0 35-C44-23 ' 
, QI2-I5 =0 35- 045-6 < 


► 4I-A49-4 


I4I-A49-25 


I 4I-A49-II 


1 73- 062- 9 
17^ A62-6 

I73-A6I-I7 ^Y00-04*0 
4I-A42-24 
147-B6I-22 J 


006-n =0 35 - 046-23 ' 
000-05 = 0 35- 047-23 1 


AI5 

35- C42-I8 


SEL SKIP 
SWITCH SET 
17 - E64-I4 * 


OVERFLOW 

57-036-1 

STORAGE PARITY ERROR 
101 -A34-2I 

PROGRAM PROTECT FAULT(| 
69-A35-27 

X5 

39- B44-I I 
X6 

39-B44-I0 

X7 

39-B44-3 












ADDER CONTROLS (XR AND LP) 


The Exclusive OR (XR) and Logical Product (LP) control FFs enable the 
corresponding logical operations on the Adder/ Shifter modules. The XR and LP 
FFs are contained on the V38 module. The inputs to the corresponding inverters 
on the V39 module specify the conditions for setting and clearing XR and LP. 

EXCLUSIVE OR (XR) CONTROL 

When set, the XR FF enables the Exclusive OR(A-V*B) function in the Adder/ 

Shifter. The Exclusive OR can take place between two operands, as in an IR 
instruction, or between an operand and all "I's", as in complementing a negative 
operand in the Multiply instruction. Examples of both cases are shown below: 

15 14 13 12 11 10 - - - - 0 Bit Positions 

1 0 1 1 0 1----1 Operand A 

0 1 1 0 1 1----0 Operand B 

110110 1 Result 

15 14 13 12 11 10 0 Bit Positions 

1 0 1 1 0 1----1 Operand A 

1 1 1 1 1 1 1 All "I's" for Operand B 

0 10010 0 Result 

In both examples, a '*1" appears in the result only when a "l" is in a certain bit 
position of one operand and a "0" in the same bit position of the other operand. 
Thus, a "l" results when a "l" exists in operand A or B but not in both. In the 
second example, all "I's" are used as a mask to complement operand A. In this 
way, a number can be converted to the ones -complement equivalent. The second 
example shows a negative number (operand A) converted to its positive equivalent 
through the XR function. 

The XR FF has two Set/Clear gates (A, B and C, D) and one Clear gate (E). The 
A, B gate sets XR at VlOO time while the C, D input sets the FF at V300 time if 
one of the corresponding inverter inputs is satisfied on the V39 module. Inverter 
E clears XR at V200 time if the input to the corresponding inverter on the V39 
module is satisfied: (MUI) (SRI) (C CYCLE) + (DVI) (YOO-04 = 0) (SR 2) (C CYCLE). 

A typical XR operation for the first example is had by assuming an IR instruction 
in the REG mode, A cycle enabled and bit Xg of the instruction code set. The 


setting of Xg specifies an XR operation between the operands in the origin registers 
(Xg, X^, and Xg). In this case, XR is set at VlOO time (B, C) and the Exclusive 
OR function is enabled in the Adder/ Shifter modules. When the selected operands 
are gated into the Adder/ Shifter, the Exclusive OR operation takes place. 

An XR operation for the second example takes place during the A cycle of the 
ROP mode for a DVI instruction with SR 2 set. In this case, the initial dividend 
is negative (SR 2 set) and (Q) is complemented prior to the first divide step. Thus, 
XR is set at V300 time (C, D). Since (Q) is now gated to the addend gates while 
all "I's" are enabled into the augend gates, the XR enable complements the (Q) in 
the Adder/ Shifter. 

LOGICAL PRODUCT (LP) 

The setting of the LP FF enables the Logical Product (AND) function on the 
Adder/ Shifter modules. The LP function takes place between two operands, as 
in IR or AND instructions, or between an operand and all "I's" to enable a 
straight-through transfer of an operand through the Adder/ Shifter, as in a 
Multiply instruction. Examples of both cases are shown below: 

15 14 13 12 11 10 0 Bit Positions 

101101 1 Operand A 

1 1 1 1 0 0----0 Operand B 

1 0 1 1 0 0----0 Result 

15 14 13 12 11 10 - - - - 0 Bit Positions 
1 0 1 1 0 1----1 Operand A 

1 1 1 1 1 1 1 All "I's" for Operand B 

1 0 1 1 0 1----1 Result 

In both examples, a "l" appears in the result only when a "l" exists in 
corresponding bit positions of the two operands. Thus, a "l" results when a 
"l" exists in operand A and B, 

The LP function is often used to mask out certain portions of an operand, as in 
the first example. In this case the low-order 12 bits of operand B are all "O's", 
and the high- order 4 bits are all "I's". Thus, all but the high-order 4 bits of 
operand A are masked out. 

44.1 
Rev. A 



ADDER CONTROLS (XR AND LP) (Cont'd) 


For example, assume an AND instruction in the ROP mode, B cycle, and VlOO 
time (HOI) (tOO). In this case, the operand read from storage (X) and the operand 
in A transfer to the Adder/ Shifter simultaneously with the setting of LP. As a 
result, LP enables a Logical Product operation in the Adder /Shifter between the 
two operands. 

The LP function also enables a straight-through transfer of an operand through the 
Adder/ Shifter. In this case, all the bits of one operand are "I's". Thus, operand 
A transfers through the Adder /Shifter either unchanged or shifted right or left. 

An example of this type of LP operation is had by assuming a Multiply instruction, 
C cycle, and VlOO time (HOI and tOO). These conditions set LP simultaneously 
with the transfer of (A) -»• Adder. Since the Shift-Right control was previously set, 
LP enables the (A) to be shifted one place to the right. 


The LP FF has two Set gates and two Clear gates. The Stopped mode sets LP 
through inverter H*. The setting of LP at this time enables the transfer of the 
manually selected register output through the Adder /Shifter. 

The other Set gate is enabled at tOO time if the input conditions to one of the 
corresponding inverters on the V39 module are satisfied. Three of the inverter 
gates are enabled at VlOO time (HOI and tOO) while the remaining gate is enabled 
at V300 time (H05 and tOO). 

The output of inverter E clears LP at V200 time (H03 and tOO) simultaneously 
with XR. Inverter E is enabled at the termination of the C cycle of a Multiply 
or Divide instruction. The other Clear gate to LP is enabled at V300 time (HO 5 
and too) if the input conditions to one of the corresponding inverters on the V39 
module are enabled. For example, LP is cleared during the B cycle of each 
ROP mode at V300 time. 


44. 2 
Rey. A 



k 

3 



j 2 | 




t 


^ 




too 

3-B62-I3 

H03 

\ 7-A38-2 

-V 

\ 



I (REG)(IR)(X6)(X7) 
? 57-D36-20 


too / 

3-B62-J2 ' 


FROM 

DISPLAY ' 
7- B35-I9^ 


HOI 7- C43-3 < 
too 3- B62- 15 ( 
H05 7-045-2 ( 


>5^C56:_9_ 
>^B^:_9_ 
>3- A56-9 


23161 -A55-9 

"2^61-955-9 

~2^59-C55-9 
"ztX'sT- D55-I7 


LOGICAL PRODUCT (LP) 


t 6^-DJ6-l7_ 

6^B56-I7_ 

63-A56-I7 


_6l 6h- A_55 -17_ 
_4Y6I_-BJ5-I^ 
_[Y5?_-CJ5- I^ 
TX 57-055-22 



il^ CONTROL DATA 
m CORPORATION 

TITtI 

ADDER CONTROLS 

COMPUTER DIVISION 

(XR+ LP) 





ADDER CONTROLS (SHIFT) 


The Shift Adder Controls enable the left or right Shift operations on the Adder/ 
Shifter modules. These controls consist mainly of the Right Shift (RS) and Left 
Shift (LS) FFs, the Set/Clear input conditions, and the fan-outs for these FFs. 

The RS and LS FFs and the input Set/Clear enables are contained on the V37 
module. The RS, LS, and shift fan-outs to the Adder/ Shifter modules are con- 
tained on the V23 module. 

The RS and LS FFs ape set and cleared under similar conditions. In Shift cycle 
operations, RS or LS is set by inverter F at V325 time (t25 and H06) in the A 
cycle. If bit 7 (X,^) of the instruction code is a "l" at this time indicating a Left 
Shift, inverter 1 enables the setting of LS. If Xrj = "O", RS is set. 

The RS or LS FFs are cleared by inverter F in the C cycle. Since H06 is not 
set in the C cycle until V300 time of the last shift cycle, the clearing of LS or RS 
at this time indicates the completion of the shifting operation. 


In Multiply operations inverter F sets RS in the A cycle of the ROP mode. Since 
H04 is not set until V200 time of the C cycle for the last multiply iteration, 
inverter E clears RS at V225 of the last multiply iteration. 

In Divide operations, inverter E sets LS at VI 00 time (H02 and t25) of the C qycle 
for each divide iteration. Inverter F clears LS at V325 time of each iteration. 
When Yqq_q 4 = 0 indicating the divide is complete, inverter E clears LS at V225 
time of the last iteration. 

The V23 module provides eight outputs for the RS and LS enables. One output 
from each connects to each of the Adder/ Shifter modules. The V23 module also 
provides the shift enable to the Adder/Shifter module. If either the RS or LS 
is set, inverter E or F on the V23 module enters a "0" in the shift enable 
fan-out. As a result, the shift enable becomes a "0", 


46 

Rev. A 








ADDER GATE CONTROLS 


The Adder Gate Control FFs enable the input to the augend and addend gates 
according to the translaged conditions of the instruction being executed. Only 
one input is enabled to the augend and/or addend gates at a tinae. If no input 
is enabled to the augend or addend gates, the corresponding adder inputs 
receives -0. This input enables the adder to add -0 to the other input, such 
as in a simple register transfer, to perform an exclusive OR, or logical 
product function. 

AUGEND GATES 

Four FFs control the inputs to the augend gates: A - Adder, +1 — Adder, 

Y - Adder, and X - Augend. The block diagram (p.l ) shows that these four 
quantities enter the augend gates. Since the X register enters both the 
augend and addend gates, a separate FF controls the entry of the X register 
to the augend and addend gates. 

The Augend Control FFs are contained on two V04 modules. The FFs are set 
at VlOO (HOI and tOO) or V300 time (H06 and tOO). The manual selection of 
A or Y for display enables the setting of the corresponding control FF at 
time too. For example, if A is manually selected, the manual input becomes 
a "1". The Stopped condition of the computer partially enables inverter I. 

The too pulse produces a "1" output of I which sets the A - Adder FF. As 
a result, the contents of A are displayed on the indicators connected to the 
Adder outputs. 

On Multiply (MUI) or Divide (DVI) operations, the A-»- Adder FF is cleared 
on every V200 time of the C cycle by inverter O. 


A- ADDER 

The A Adder FF gates the outputs of the A register to the augend gates of 
the Adder/ Shifter when set. The conditions determining the setting of this 
FF are enabled at the inputs to the two groups of inverters on the V35 module. 

For example, during each shift cycle of a Shift A instruction, the V300 
pulse sets the A-v Adder FF on both the A cycle and C cycle. This function 
gates the contents of the A register into the Adder/ Shifter for the Shift 
operation. 

For another example, assume that the X 5 bit of the IR instruction is set, 
designating A as the origin register for the inter-register transfer. Thus, 
in the A cycle portion of the REG mode, the VlOO pulse sets the A— Adder FF, 
enabling the transfer of the contents of the A register to the Adder/Shifter. 


The Command Timing Sequences list the specific conditions and times for the 
setting of the A — Adder FF for the applicable instruction. 

+1 - ADDER 

The setting of the +1 — Adder FF gates a +1 input to the augend gates of the 
Adder/Shifter. This input is used mainly to add one to the address of the 
present instruction (P) to get the address of the next instruction. For example, 
during the A cycle of the ROP mode of all instructions except EXI, MUI, or 
DVI, the V300 pulse sets the +1 — Adder FF which initiates the advancing of P 
for the next instruction. The Block +1 function inhibits, through inverter D, the 
setting of the +1 — Adder FF which initiates the advancing of P for the next 
instruction. The Block +1 function inhibits the advancing of P under certain 
instruction conditions, such as after Clear P or an internal reject. 


In the B cycle of the ADR mode in the RTJ instruction, the +1 — Adder FF is 
set at VlOO time. This function performs the P + 1 function which is stored 
at the effective address. The P + 1 value represents the return instruction 
address following the completion of the subroutine. 

Y - ADDER 

The Y — Adder is used mainly in address modification functions. In this case, 
the quantity in the Y register which represents base address or partially 
formed effective address is gated to the adder. The adder adds the quantity 
to another value in order to form the final effective address. 

For example, assume the following conditions: (ADR) (INT) (ind) (q) 

(A cycle). Thus, in an indirect address function, the contents of the Q register 
(q index) is added to the base address ( A in the Y register) to form the 
effective address. In this case, the V300 pulse sets the Y - Adder FF which 
gates the contents of the Y register to the augend gates. Simultaneously, the 
contents of the Q register transfer to the addend gates. 

X - AUGEND 

The setting of the X - Augend FF gates the contents of the X register to the 
augend gates. The inputs to the corresponding inverters on the V34 module 
specify the conditions for setting the X — Augend FF. 

For example, in the C cycle of the Mult. Step operation with MB = 1, the 
X — Augend FF is set at V300 time. This function transfers X to the augend gates 
while the simultaneous setting of the Q — Adder FF gates Q to the addend gates. 
Thus, Q (partial product) is added to X (multiplicand) which produces the next 
partial product or final product in the case of the last Mult. Step. 


48 

Rev. aA 



SHIFT CYCLE (A)(Q) 
73-D62-25 ‘ 


DVr+MUI+SPA+STA X\ 
27-D50-9 
REG[jR(X5)+ INAn 
25- A5I - 2 
SHIFT CYCLE (A) ilO 
73-062-23 
{ROP) MUI+DIV. STEP 
29-A57-8 


(ADR)C(READ INDEX) + (r){RNI fA?40)] 
I3-B39-I9 
JUMP Is? 

27-050- 28 Yd^ 
INT. + RTJ 1 15. 
29-C5I-I4 


A CYCLE 
B CYCLE 
C CYCLE 

aM 

STO I 


I I - E52-4 

II - E5I-2 
II - E53-3 
9- A40-26 
9 - C59-I 


MANUAL SELECT A 
15 - 063-16 


SEE P. 7 I 
859 

.A |V341 


^ H05 7-045-24 

/ too 3-B62-I 

I HOI 7-C43-28 

/ 

/ FROM DISPLAY 7-B35-9 

/ too 3-B62-2 

, (MU1 + DVI)(H03){C-CYCLE) 
' 51-059-26 



A-*- ADDER 
3I-C4I- 15 


53-053-28 
53- B53-28 
53- A53-28 
53 C53 28 


(SHIFT CYCLE) 
73-062-21 


(RNIHFII) 
13-B39-I6 ' 

(ROP) RAO 
29-C5I-22 ' 
RTJ , 

29-A57-25 ' 

RNI (A = 0)(ADR) , 
13- B39-23 ’ 
(SPA)(A80RTEDI) 
29- A57-28 


DIV. STEP + (MULT. STEP)(MB = I) 
73-A6I-I0 

[mUI (MB=I ) + EXf] ( ROP) , 


(ENQ+SKIP + INQ-FINP-I-OUT) REG) 
25- 851-13 
(INT) (A = 0) 
13- 057-28 

(ROP) ADO 
27-051-9 


A CYCLE II-E52-3 

B CYCLE II-E5I-I 
C CYCLE II-E53-4 
8LK + I I9-A63-26 
Weg 9-C39-I0 
A^ 9-A40-25 
STOl 9-C59-4 


EXTEND SIGN REG 


(SKIP + EXI) +RNI(FII)(ADR) 
39-B44-4 


^ rr 

^ (ACYCLE)(ADR)(TNT){ind)(q)(RNI +A/0) l|0 

/ \ 51-059- I 

/ \ (A _CYCLE_) 1 b"^ 

* MANUAL SELECT Y 

15-063-1 V ’ 


H05 7- 045-26 

too 3-B62-6 
HOI 7- C43-26 

FROM DISPLAY 7-B35-I8 
too 3-B62-7 
1.2V 43-A39-4 



53-053-22 
53- 853-22 
53- A53-22 
53-C53-22 

Y-»» ADDER 
41 - A42-2 


53- 053-14 
53-B53-I4 
53-A53-I4 
53-C53-I4 


TO AUGEND GATES 


TO AUGEND GATES 


CONTROL DATA 

TtTLt 

corporation 

ADDER GATE CONTROLS 

COMPUTER DIVISION 

(AUGEND) 



ADDER GATE CONTROLS (Cont’d) 


ADDEND GATES 

Four FFs control the inputs to the addend gates: Q ^ Adder, X -^Addend, 

P -►Adder, and Mask - Adder. Thus, the setting of one of these FFs 
transfers the output of the corresponding register to the addend gates of the 
Adder/ Shifter. Only one of the Addend Control FFs is set at a time. If 
none of these FFs are set, the addend gates receive an input of all 

The Addend Control FFs are contained on two V04 modules. The FFs are 
set at VlOO (HOI and tOO) or V300 (H05 and tOO). The manual selection of 
Q, X, P, or Mask for display enables the setting of the corresponding 
control FF at time tOO. The FFs are set in the display condition in the 
same manner as the Augend Control FFs. 

The Command Timing Sequences list the times and specific conditions for 
setting the Addend Control FFs. 

Q - ADDER 

When set, the Q — Adder FF gates the output of the Q register into the 
addend gates of the Adder/ Shifter. The inputs of two groups of inverters 
on the V33 module establish the conditions for setting the Q — Adder FF. 

An example of the setting of the Q — A dder FF is made by assuming the 
following conditions; (ADR) (INT) (ind) (q) (RNI -t A= 0). Thus, the 
contents of Q (q index) are added to the base address to form the effective 
address. At V300 time of the A cycle (H005 and tOO), the outfiut of 
inverter J on the V04 module sets the Q — Adder FF. 

During MUI or DVI operations, the Q — Adder is set at the V300 time of 
the A cycle during the ROP mode. In a Multiplication operation, this action 
initiates the initial adding of Q to the multiplicand in X if MB is set. On 
each following Mult. Step. , the Q — Adder FF is reset at V300 of the C cycle. 


X - ADDEND 

The inputs to the four corresponding inverters on the V33 card specify 
the conditions for setting the X — Addend. For example, the VlOO pulse 
sets the X - Addend FF on every A cycle of the ROP mode. 


In addressing operations RNI ( A = 0) (ADR), VlOO of the A cycle sets the 
X — Addend FF. This operation transfers the base address in X to the 
adder for possible address modification. 

P - ADDER 

The setting of the P — Adder FF transfers the current program address 
in P to the adder for modification. In most cases, a +1 is added to P to 
obtain the address of the next sequential instruction. Thus, at V300 of 
the A cycle in the ROP mode of all instructions except EXI, MUI, or DVI. 
the P — Adder FF is set simultaneously with the -t-1 — Adder (augend gates) 
which adds -Hi to P. 


The V300 pulse sets the P — Adder FF in the A cycle of the STO mode of 
every applicable instruction. The P - Adder FF is also set at the V300 
time of the A cycle in the REG mode of every applicable instruction 
except during Shift Cycle operations. 

MASK - ADDER 

The Mask — Adder FF is set at VlOO time of the A cycle only on IR 
instructions when bit 3 of the X register is set (Mask is origin register). 
In this case, the contents of the Mask register transfers to the addend 
gates of the adder for subsequent transfer to the selected destination 
register. 


50 

Rev. A 




Q«* ADDER 


CSS 

1 ^ 




ADDER /SHIFTER FAN-IN GATES (AUG) 


The augend (AUG) gates of the Adder /Shifter receives enables from the augend 
adder gate controls which enable the inputs from the corresponding register. 

Thus if the X Augend FF on the augend gate control module is set, the X -► 
Augend input to each of the AUG gates becomes a "O", The resulting ”l" output 
from inverter A enables the inputs from the X register into the corresponding 
inverters on the AUG gate modules. 

The AUG gates are contained on four VO 3 modules. The bit positions on each 
module are divided in pairs according to the chassis locations of the V03 module 
and the adder/ shifter module to which they connect. For example, bit positions 
1 and 2 are on the VOS module at location C53, Bit positions 1 and 2 for the 
Adder/Shifterare on the VOO module at location C55. This system is used to 
reduce the lengths of the connecting wires between the two modules to a minimum. 


Each bit position on the V03 modules consists of four input inverters and a True 
and Not' output inverter. When one of the enables from the augend gate controls 
in a "0", the corresponding inverter (A, B, C, or D) enables the corresponding 
bit position inputs. The "l” inputs from the selected register produce "l” outputs 
on the AUG — lines and "O” outputs on the AUG — lines. If none of the enables is a 
"O" indicating that no input is selected for the augend gates, inverter E produces 
a "O" output. All the AUG—— outputs now become "I's" whenever no input is 
selected for the AUG gates. 

In the case of a +1 Adder selection, inverter D enables a GND ("l") input to 
bit position 0 and 1.2v ("O") inputs to the remaining bit positions. Thus, the 
Adder /Shifter receives a +1 input from the AUG gates. 


Rev. A 












ADDER/ SHIFTER FAN-IN GATES (ADN) 


The addend (ADN) Adder/Shifter fan-in gates receive enables from the addend 
adder gate controls which enable inputs from the corresponding register. If a 
particular Addend Adder Control FF is set, the enable to the ADN gates becomes 
a "0", The output of the corresponding inverter (A, B, C, or D) enables the 
input from the selected register into the ADN gates. The True and Not outputs 


of the ADN gates connect to the Adder/ Shifter modules. 

The ADN gates function in the same manner as the AUG gates as described 
on page 53. 


54 

Rev. A 














GROUP 0 OF ADDER 


ADDER LOGIC 

The adder portion of group 0 is contained on the V60 module. The 
adder logic functions on this module in an identical manner to the equivalent 
logic on the other groups of the adder (page 59 ). However, in place of the 
group borrow input, the V60 module receives the Section 1 Borrow + ( Section 
0 Borrow) (Section 1 Enable) conditions. Thus, group 0 of the adder receives 
a group borrow input from a Section 1 Borrow or from a Section 0 Borrow and 
a Section 1 Enable. 


3210 Bit Positions 

0111 Augend (+7g) 

0111 Addend (+7g) 

1111 Stage Difference 

11 10 -^Borrow Corrected Difference (-1) 
EAB J 


Positive Overflow 


End Around Borrow (EAB ) 

A stage 15 borrow (H) or a stage 15 enable (El 5) and a group borrow 
input corresponds to an EAB condition. In the V60 module, the EAB functions 
the same as a stage borrow in the other modules since stage 0 is contained on 
the same module. 

OVERFLOW 

The V60 module detects the Adder Overflow condition. The Adder 
Overflow occurs when the result of an arithmetic operation exceeds the mod- 
ulus of the adder in the ones complement system. An overflow can occur in 
the positive or negative direction. The overflow condition can also be 
expressed logically as follows; 

Overflow = (S15B) (Bit 15=”l") + (Bit 15="o") (S15S) 

S15B - Stage 15 borrow 
S15S - Stage 15 satisfy 

The^irstJ:wo terms correspond to a positive overflow and the second two 
to^ negative overflow. Simplified examples of both types are as follows. 


3210 

1000 

1000 

1111 


Bit Position 
Augend (-7g) 

Addend (-7g) 

Stage Difference 

Borrow Corrected Difference (+1) 


Negative Overflow 

In the first example, the sum of the two positive numbers exceeds 
the modulus of the simplified adder. This condition corresponds to the first 
two terms in the logical equation above. Thus, the detection of an EAB and 
a "l" in stage 15 of the sum denotes a positive overflow. 

The second example shows a negative overflow, In this example, the 
sum of two negative numbers exceeds the modulus of the simplified adders. 

A negative overflow is detected when bit 15 is a "O" (positive result) and bit 
15 of the augend and addend produce a satisfied conditign. 

The detection of an overflow on the V60 module produces a "O" output 
on pin 27. The enabling of either the two main input gates sets the Overflow 
FF (H) on the V58 module. For example, V275 (H005 and t75) sets H on the 
B cycle during the ROP mode on an ADD Instruction if an overflow is detected. 

In an Inter Register instruction, the setting pf bits 6 or 7 (Xg or X^) of 
the instruction code denoting an Exclusive Or or Logical Product disables the 
setting of H. Thus, the setting of H is disabled unless the overflow resulted 
from an arithmetic Add or Subtract operation. 


56. Q 
Rev. p 



GROUP 0 OF ADDER (Cont'd) 


An overflow can also result from a divide instruction. In this case, 
an overflow results wheh the quotient in the A-register becomes negative 
at the completion of the Divide operation (Divide Step). An overflow during 
a Divide instruction occurs when the answer exceeds the modulus of the 
16-bit register. 

The Overflow FF is also set at V275 time of the A cycle during an 
Exit Interrupt (EXI) instruction if bit 15 of the word read from storage 
(containing the return address) is a "1". A "l” in this position denotes the 
Overflow FF was initially set at the time the interrupt occurred. If is 
a "0" at this time, H is cleared. 

In an Interrupt operation (INT), the state of the Overflow FF trans- 
fers to bit 15 of the addend gates. The P -♦Adder command is also enabled 
at this time. Since the P register now contains the return address for the 
EXI instruction, the state of the Overflow FF is combined with the return 
address. 

The Sense Overflow command during a Skip instruction clears H at 
V2 75 of the A- cycle. The setting of the Overflow FF also lights the 
Overflow Fault indicator during thb Display mode. 

SHIFTING OPERATIONS 

Shifting operations for group 0 of the adder take place on the V61 
module. Left or right short shifts take place in the same manner as in the 
other groups of the adder. In the case of left shifts, which are always end- 
around, bit 15 transfers from pin 21 to the V60 module to pin 14 of the V61 
module. The LS enable shifts bit 15 to the bit 0 output. Bit 0 transfers 
from pin 16 of the V60 module to the group 1 VOO module (page. 59). The 
LS enable shifts bit 0 to the bit 1 output. 

All right shifts (RS) are end-off. Thus, bit 1 shifts to the bit 0 
output of the V61 module. The bit 0 output is not used in RS operations. Bit 
15 transfers from pin 23 of the V60 module to the group 7 VOO module (page 
65). The RS enable shifts bit 15 to the bit 14 output. Since it is assumed 
that the LRS2 and MUI controls are not enabled in this case, bit 15 transfers 
to the bit 15 output of the V61 module, extending the sign. 


Long Shift 

A long shift takes place when both bits 5 and 6 of the Shift instruction 
are "l", indicating that both A and Q are to be shifted, A long shift also 
takes place for each iteration of a Multiply or Divide instruction. In any of 
these instructions, VI 25 (t25 and H02) sets the Long Shift FF. The setting 
of the Long Shift FF enables a LLS2 or LRS2 operation depending on whether 
a left or right shift is selected. 

Long Left Shift (LLS): The LLS operation takes place in two steps; LLSl 
and LLS2. The LLSl operation is enabled by the following conditions: 


LLSl = (MUI + DVI .+ Shift QA) (Long Shift) ( LS) 

Thus, LLSl takes place before the setting of the Long Shift FF, which 
enables LLS2. 

In a typical LLS operation (fig. 1, page 56.^2), .Q is shifted first followed 
by the shift of A. In the shift of Q, LLSl enables the shift of bit 15 of A 
directly to the output of bit 0 of Q on the V61 module. At VI 00 time (tOO 
and HOI), Q15 transfers from the V60 module to set the Bit Bucket FF. The 
Bit Bucket FF retains the state of Q15 until the shift of A. At VI 25 time, 
the Long Shift FF is set which disables LLSl and enables LLS2. The LLS2 
enables the shift of the bit bucket to bit 0 of the shifted A output. 

During Divide Step operations, the detection of the EAB condition 
which indicates that (Q) > (X) sets the bit bucket at VI 00 time. The 
contents of the bit bucket is shifted to bit 0 of the shifted A output. 

Long Right Shift (LRS): The setting of the Long Shift FF enables LRS2. The 
LRS2 output enables the shift, of the state of the bit bucket to the bit 15 output 
of A. 

During (QA) or MUI operations, bit 0 of Q-transfers to the bit bucket 
on the shift of Q. Bit 0 subsequently shifts from the bit bucket to bit 15 of 
the A output. Fig. 2, page 56, 2, shows a simplified illustration of a LRS 
operation. 


56. 1 
Rev. A 



15 14 


SHIFT 


Fig. 1 






V58 




ADDER/SHIFTER 


The block diagram in Figure 1 to. the right shows that the Adder/ Shifter circuit is 
divided into three main divisions: 

1) Adder/Shifter modules (VOO) - perform stage borrow and enable, 
shifting. Exclusive OR, and Logical Product functions. 

2) Borrow Look - Ahead modules (VIO) sense stage borrow and 
enable conditions. The VIO modules produce group borrow and 
section borrow and enable conditions. 

3) Fan-out modules (V06) provide the required number of outputs from 
the Adder/ Shifter to the registers indicated, 

ADDER PYRAMID 

One of the main functions of the Adder/ Shifter is the adding operation. The 
adder is divided into eight groups. Each group is contained on a VOO module. 

All groups except group 0 are logically identical. Thus, the following descrip- 
tion is based on the operation of a typical group of the adder (group 1). The 
basic logical operation of group 0 is similar to the other groups. However, 
this group contains some additional features and is described separately on 
page 56. 1, 

STAGE BORROWS AND ENABLES 

Figure 3 shows that each group operates on two adjacent bits of the addend 
and augend. (Bits 0 and 15 are considered adjacent bits in the adder pyramid.) 
Thus, group 1 compares bits 1 and 2 of the augend and addend. 

The adder pyramid uses a subtractive pyramid circuit to perform the Add 
function: AUG - (-ADN) = AUG + ADN = SUM. The principles of a subtractive 
pyramid are shown in Figure 4. 

A stage borrow results whenever a "l" is subtracted from a "O". Thus, in 
Figure 4, the borrow generated in stage 0 propagates to stage 1 where it is 
satisfied. Enables result when a "l" is subtracted from a "l" or a "O" from 
a "0". Enables propagate borrows but are toggled as a borrow passes through 
as shown in Figure 5. 


ADDER /SHIFTER 
MODULES (VOO) 
(STAGE BORROWS 
a ENABLES) 



Figure 3, Adder/Shifter Block Diagram 


58.0 
Rev. A 







ADDER/SHIFTER (Cont'd) 


Figure 4. 


0 0 0 1 


STAGE NO. 

MINUEND 

SUBTRAHEND 


3 2 I 


1 

STAGE DIFFERENCES 

0 

1 

1 

0 

[_ 

BORROW 

0 

1 

0 

1 


1 

1 



SATISFY 


ENABLES 

BORROW CORRECTED DIFFERENCE 
( + 6) - (+5) = + I 


Principles of a Subtractive Pyramid 


ri I 0 0 

L — ► _i 

END AROUND 
BORROW 


STAGE NO. 

MINUEND (AUGEND) 

SUBTRAHEND (ADDEND) 

STAGE DIFFERENCES(PARTIAL SUM) 

ENABLES 

SATISFY 

BORROW 

BORROW PROPAGATION 

BORROW CORRECTED DIFFERENCE 

(+6e) - ('5 b) = + 130 SUM 


STAGE NO. 

MINUEND 
SUBTRAHEND 
STAGE DIFFERENCES 

BORROWS 
ENABLES 

BORROW PROPAGATION 
BORROW CORRECTED DIFFERENCE 
( + 4) -( + 7) = - 3 

Figure S. Example of Borrow Propagation 

Figure 5 shows that the borrow generated in stage 0 propagates to stage 1 which 
it toggles. Stage 1 also generates a borrow which propagates through enables 
at stages 2 and 3 which are toggled. The end-around borrow toggles the stage 0 
difference which produces the final difference. 


3 2 10 


0 10 0 
0 111 



r l<- 1 <-o <-1 
; I I 0 0-^ 

END AROUND 


Figure 6. Principles of the Adder Pyramid 

Because the addend bits are complimented in the bit comparisons. Figure 6 
shows that a "l" subtracted from a "O" or a "O" from a "l" produces an enable. 
The subtraction of a "l" from a "l" results in a satisfy while the subtraction of 
a "o'’ from a "O" produces a borrow. All other logical conditions for a subtractive 
pyramid apply to the adder. The example in Figure 6 shows the final sum of 
+13g for the quantities used. 

The stage borrow and enable conditions are sensed at the input inverters on the 
VOO modules. The enable for stage 1 (SIE) is defined by the following logical 
equation: SIE = [(AUG 1) (ADN 1) + (ADN 1) (AUG 1)] ( LP ) 


If the LP term is disregarded in this case, the SIE condition is sensed when the 
corresponding bits in the augend and addend are unlike. This logical arrangement 
corresponds to the example in Figure -U.. 

The stage 1 borrow (SiB) is defined by the following equation: 


Since the output of the subtractive pyramid is a sum, the ADN inputs are 
complimented in the stage comparisons according to the principles shown in 
Figure 6. 


SjB = (AUG 1) (ADN 1) (LP) 


58.1 
Rev. A 






ADDER/SHIFTER (Cont'd) 


Disregarding the LP term, a stage borrow results when corresponding bits in 
the augend and addend are both "O's", which also corresponds to Figure 6. 

The stage borrow and enable conditions are sensed in the same manner on all 
VOO modules. 

Borrow Propagation 

The propagation of borrows in the VOO modules takes place in the following 
three ways; 

1) Borrows generated by the low-order adjacent stage within a group. 

2) Borrows generated by the high-order stage within a group 
(group borrow). 

3) Borrows generated by the adjacent lower-order group. 

A case 1 borrow propagates directly to the adjacent stage in the group, regard- 
less of the group borrow input to the generating stage. For example, assume 
a borrow input to stage 1 of group 1 exists. Inverter produces a "O" output 
which propagates the borrow directly to stage 2 through the interconnecting 
inverter, regardless of the group 0 borrow input. 

Case 2 borrows are transmitted to the group borrow logic on the corresponding 
VI 0 module through pin 8 on the VOO module. For example, assume a borrow 
input to stage 2 of group 1. The S 2 B output on pin 8 becomes a "O", indicating 
a stage 2 borrow. The S 2 B condition corresponds to a group 1 borrow which is 
described in more detail in a subsequent paragraph. 

The case 3 borrows probe the enable condition of the low-order stage in a 
group. If an enable exists in that stage, the output of that stage becomes a 
” 1 '* (toggled) and the borrow is propagated to the adjacent stage in the group. 
For example, assume a group 0 borrow input to group 1. The group 0 borrow 
input probes the output of inverter E]^ through the interconnecting inverters. 

If an enable exists in stage 1, E^ produces a "l" output and the group 0 borrow 
propagates to stage 2 where it probes the E 2 output. If the group borrow 
probe detects an enable in a stage, it forces the output of that stage to a "l" 
corresponding to the toggling of the "O" output in the partial sum. 


GROUP BORROWS 

Each group produces three outputs to the corresponding section (VIO) module. 
These outputs determine whether a borrow is generated by the corresponding 
group. For example, group 1 produces the S 2 B, (S^B) (S 2 E) and (SjE) (S 2 E) 
conditions from pins 8, 1, and 3 respectively. 

The corresponding VIO module generates group borrow, section borrow, and 
section enable outputs according to the enable and borrow condition of the 
groups in that section. The section 0 module, for example, generates group 
borrows for groups 0, 1, 2 and 3. The group 3 borrow corresponds to the 
section 0 borrow. The following logical equations represent the group borrow 
function for a typical group (group 1) in section 0. 

Group 1 Borrow = [S2B + (SIB) (S2E)] + [(SIE) (S2E) (SOB) + (SIE) 

(S2E) (SOE) (S15B)] + [(S15E) (SOE) (SIE) (S2E) (J)] 

J (Section 0 Borrow Input) = Section 1 Borrow + (Section 1 Enable) 

(Section 0 Borrow) 

The equations above show that in general a group borrow results when any of 
the following conditions are present: 

1 ) The higher-order stage in the group generates a borrow. 

2) The higher-order stage in the group produces an enable and the 
lower order stage in the group generates a borrow. 

3) A stage in a lower-order group generates a borrow and all higher- 
order stages in all groups up to and including the generating group 
produce enables. This condition is represented by the third term 
in the group 1 borrow equation. 

The group borrow outputs go to the next higher- order group. 

SECTION BORROWS 

The section borrows are generated on a VIO module when a borrow propagates 
through all the groups in a section. For example, the borrow can either originate 
in section 0 or originate in section 1 and propagate through section 0. 


58.2 
Rev, A 



ADDER/SHIFTER (Cont'd) 


Section borrows are generated under the same conditions as a group borrow. Thus, 
the section borrow can also be termed the group 3 borrow because group 3 is the 
highest order group in section 0. Figure 7 shows a simplified example of a section 
borrow. 

In Figure 7, the borrow originates in group 3 and propagates to section 1 as the 
section 0 borrow. Since all the groups in section 1 generate enables, the borrow 
propagates through section 1. The combination of a section 1 enable and section 0 
borrow enters a borrow input to section 0. 

SECTION ENABLES 

Each section generates a section enable when all the groups in the section produce 
enables. In Figure 7, section 1 generates an enable because groups 4-7 all 
produce enables. 


BORROW "O" 



NOTES : 

B- REPRESENTS GROUP BORROW 
E- REPRESENTS GROUP ENABLE 


Figure 7. Simplified Section Borrow 


ADDER OUTPUTS 

The output of the B-inverters on the VOO modules represents the output of the 
corresponding stage of the Adder, For example, B^ on the group 1 module 
represents the output of stage 1 of the Adder. The Adder’ outputs connect to the 
Shifter circuit, to the corresponding indicator light and to the fan-out module. 
The logical equation below represents the conditions for a typical Adder output. 

Bj = (El) (Group 0 Borrow) (LP) + (Ej) (XR) + (XR) (LP) (AUG 1) 

(ADN 1) + (XR) (Group 0 Borrow) (LP) (AUG 1) (ADN”i) 

By assuming (LP) (XR) conditions, the above equation becomes: 

Bi = (Ej) (Group 0 Borrow) + (Group 0 Borrow) (AUG 1) (ADN 1) 

Thus, stage 1 of the Adder produces a "l" output with a stage 1 enable and a 
group 0 borrow or a stage 1 borrow and no group 0 borrow. In all other borrow 
and enable conditions, B^ produces a "O" output. With the exception of Shift 
operations, B^ represents the output of stage 1 of the Adder/ Shifter. 


LOGICAL PRODUCT 


The Adder/ Shifter modules also perform Logical Product (LP) operations. The 
LP function produces a "l" output from a stage of the Adder that corresponds 
to "I's” in the same bit position of the addend and augend as shown by the 
simplified example below. 


15 3210 

0 10 10 

0 110 0 

0 1000 


Bit Positions 
Augend 
Addend 
Result 


Setting the LP Control FF enables the input to each VOO module. Assuming an 
(LP) (XR) condition, the output of inverter A blocks all inputs to B^ except the 
input corresponding to the third term in the equation for Bj above. Thus, Bj 
produces a "l" output on an LP operation when stage 1 of the augend and addend 
both contain "I’s". 


EXCLUSIVE OR 


The Adder/ Shifter modules perform Exclusive OR (XR) functions. The XR 
function produces a "l" output from a stage of the Adder that corresponds to 


58.3 
Rev. A 










ADDER/ SHIFTER (Cont'd) 


a "1" in the same stage of the addend or augend but not both as shown 
below: 


15 - 

3 2 10 

Bit Positions 

0 - 

10 10 

Augend 

0 - 

110 0 

Addend 

0 - 

0 110 

Result 


The setting of the XR Control FF enables the XR input to all VOO modules. 
Assuming the (XR) (LP) condition, the ’*0" output of inverter B blocks all 
inputs to except the (E^^) (XR) term. Since the Ej^ output represents an 
enable condition (the bits in stage 1 of the addend and augend are different), 
Bj produces a "l" output. 


SHIFT CIRCUIT 

In a Shift operation, the operand in the A or Q register is shifted a specified 
number of positions left or right. The bits in the designated register are 
shifted one position each time the operand is transmitted through the Adder/ 
Shifter. In (QA) Long Shift operations, the operands in the A and Q register 
are shifted separately in the Shift circuit for each shift cycle. 

The shifting operation takes place on the VOO modules at the output of the 
Adder. Thus, the outputs of the B-inverters are shifted left or right one 
position. 

The setting of the LS or RS Control FFs transmits a ”0" to the Shift input to each 
Adder/Shifter module. This input disables the normal output of the B-inverters. 
Thus, the LS or RS paths determine the output of each stage of the Adder/ Shifter 
modules. 

In a shifting operation, the LP FF is set coincident with the Shift and LS 
or RS enables. Asa result, the LP input enables an LP operation in the 
Adder at the same time as the shift. The operand is gated into the augend 
or addend gates, and the gates not selected receive an input of all "l‘s". 

The output of the B inverters represents the operand. 


LEFT SHIFT 

The Left Shift takes place on the Adder/Shifter modules when the LS Control FF 
is set. The LS enable enters each Adder/ Shifter module. Since the Shift enable 
blocks the normal output of the B-inverters, the outputs of these inverters are 
enabled by the LS input. Thus, the B outputs, which represent the bits of the 
operand, appear as outputs shifted one position to the left. 

All Left Shifts are end-a round. Thus, on a Long Left Shift (LLS), the bit in stage 
15 of Q shifts to stage 0 of A. The LLS function is described in more detail in 
the Adder Group 0 section (page 57). In the Short Left Shifts, bit 15 shifts to 
bit 0, The simplified illustration in Figure 8 shows an example of a Left Shift 
operation of (A). 


15 14 13 12 II 10 9 8 7 6 5 4 3 2 I 


A REGISTER 


SHIFTER OUTPUT 



T 

ALL'*rs" 


lOIOOOl I 101 1001 0 


ADDER G 

0 1 j 0 1 j 0 0 [ 0 1 I 1 1 ] 0 1 [ 1 0 J 0 1 

1 ROUP |GR0UP|GR0UPIGR0UP IGROUPI GROUP 1 GROUP IGROUP 

7l6l5l4i3l2l 1 'O 

1 L_ 1 J_ 1 1 


J 

T 

X 

x 

XI 

X 

X 

X 

X 

X 

\ ^ i 

X 

X 


X 

X' 





_J 

] 












, 1 
















1 ADDEND GATES 1 

[ 

AUGEND GATES | 


A REGISTER 


15 14 13 12 II 10 9 8 7 6 5 4 3 2 I 


Figure 8. Example of an (A) Left Shift 


58.4 
Rev. A 




ADDER /SHIFTER (Cont'd) 


Figure 8 shows the bit positions of the Adder outputs relative to their positions 
in the groups. For example, the stage 0 output is shown adjacent to the stage 
15 output in group 0. The shift of the low -order stage of a group to the high- 
order stage takes place on the corresponding VOO module. The output of the 
high-order stage on a group transfers to the output of the low-order stage on 
the adjacent high-order group. 

RIGHT SHIFT 

The setting of the RS Control FF enables the RS input to each Adder/Shifter 
module. The Shift input disables the normal Adder output. Thus, the RS 
enable shifts the output of the B&C-dnvert-ers one -position to tha right'; All right 
shifts are end-off. Thus, the bit in stage 0 is lost. The sign bit (stage 15) 
is extended. If the sign bit is initially negative ("I*’), the stage 15 output 
remains a "l" for each shift as the other bits shift to the right. 

MANUAL SET AND DISPLAY 

The Adder/ Shifter modules serve as the means of manually setting and 
displaying the output bits of the selected register. Each manual set switch on 
the console connects to the corresponding output stage of the Adder/ Shifter 
modules. Pressing the manual set switch during the Display mode enters a 
"O" into the output inverter on the VOO module. The output becomes a "l". 

The output of the selected register enters the Adder/ Shifter modules through 
the addend or augend gates. The gates not selected receive an input of all 
"I's". In the Display mode, the LP FF is also set. Thus, a Logical Product 
operation takes place between the selected register and all "I's". The 
contents of the selected register are displayed on the indicator lights connected 
to the output of each stage of the Adder/ Shifter. The Manual Controls (see dis**- 
lay* example, .page 21) describes the manual set and display operation in more 
detail. 

FAN-OUT MODULES 

The output stages of the Adder/ Shifter connect to the output registers (A, Y, 

X, etc.) through fan-outs on the V06 modules. Each fan-out produces six 
outputs, required by the number of registers that connect to the Adder/ Shifter, 


ADDER/SHIFTER TIMING 

The Adder/Shifter operates in a static mode. Thus, the input is gated into the 
Adder at a timed period and the output is gated at a timed period. In all operations 
except short cycles (SC) the output of the Adder is gated into the enabled register 
200 nsec after the input was enabled. This delay allows sufficient time for the 
Adder circuit to stabilize. 

In most cases, the enabled input is gated to the Adder at the same time as the 
output of the Adder is gated to the enabled register. The input data does not 
interfere with the output since the minimum path through the Adder of eight 
inversions (including fan-out) is a sufficient delay. 

Figure 9 shows the Adder timing sequence for an Add to A (ADD) instruction. In 
this instruction, an operand is read from storage and is transferred to the X 
register from where it is added to the contents of the A register. The example 
shows only those commands that apply to the Adder. 

In the first Adder cycle (A cycle), the operand in the X register is gated to the 
addend gates at 100 time. However, the output is not used. At 300 time, (P) 
and +1 are combined in the Adder to give the address of the next instruction. At 
50 time of the B cycle, storage is requested which initiates the reading of the 
next instruction. At 100 time (P+1) transfers from the Adder to Y and P at the 
same time (X) and (A) are transferred to the addend and augend gates respectively. 
The output sum (A + X) transfers to the A register at 300 time. 

SHORT CYCLE (SC) OPERATIONS 

During SC operations, as in Shift and Multiply instructions, the output of the 
Shifter is gated 100 nsec after the gating of the selected input. A delay of 100 
nsec is sufficient for these operations since the full Adder circuit is not used. 
Figure l Oshows the Adder timing sequence in a Shift (A) instruction for a portion 
of one C cycle. 


58.5 
Rev. A 



ADDER/SHIFTER (Cont'd) 


A CYCLE 
( ROP MODE ) 


TIME 
(NSEC ) 



X-»> ADDEND + I -LADDER 

( NOT USED ) P-> ADDER 

(OUTPUT 
OF ADDER 
NOT 

SELECTED) 


TIME 
( NSEC ) 


B CYCLE 

( ROP-RNI MODES ) 

A 

0 50 100 200 300 0 


/ X-> ADDEND ADDER A 

REQUEST (OPERAND) (OPERAND + A ) ~> A 

STORAGE A -LADDER 
ADDER ->P,Y 
(P+ I) 


Figure 9. Example of Adder Timing Sequence in a Normal Cycle 


TIME 
(NSEC ) 


C CYCLE 
( REG MODE ) 



A ADDER A -LADDER 

ADDER ->A ADDER->A 

(RESULT OF ( RESULT OF 

FIRST SHIFT) SECOND SHIFT) 


Figure 10, Example of Adder Timing Sequence in a Short Cycle 


58.6 
Rev. A 



TO BIT 3 2) 

OF SHIFTER MANUAL 
6I-B55-24 I7-E64-7 



ADDER /SHIFTER FANOUT 
C54 

I 


FROM BIT 3 
OF SHIFTER 
6 1- B55-I2 


LIGHT (BIT2) 
Y 17- B64-22 


LIGHT IBITI) 
I7-B64-24 



REG 

3I-C50-22 A 
33-049-18 Q 
37-A44-I8 P 

39-850-27 X 
41- A49- 6 N 
7I-D44-I7 MASK 


31- C50- 23 
33-049-17 
37- A44- 17 

39-B50-I8 
4I-A49-I8 
71- D44-I6 


MANUAL 

I7-E64-I2 


GROUP 0 

1 SHIFTER, gA 

r p”=7 X 

;i4 6QAUG 15 


^ N. \ 

\ ^ \ \ 

\ ^ \ N, 

V. ^ \ \ 

^ \ V, 



3 I- C50- 24 
33- 049-28 
37- A44- 28 


71 - 044-8 
4 I - A49 - 24 
39-B50-I7 


31- C48- 5 
33- 048-2 


67- 041-26 
41- A47-2 
39-B49-28 


SECTION I 
I BORROW 


GROUPS 31 
6 a 7 
ADDER/ ^ 
SHIFTER r. 



I (S14EHSI3B)_ 

(sT«)_ YiT' 

{ SKEKSjii) 
(sT2eT(s7TbT 

(sT2Bj_ 

(sj2^(si^in 

I sT^ 

(SiOETTS9BJ_ 

Isjoe2(sje2_ 

(S7BHSJE2 

(S8B) 

(S8E)(S7E) 1|6 


jL B57 

Y26 |v|0 

BORROW INPUTS 



A55J8 ^^^^°j- - - 

GROUPS I ^ *— 

A^DDER/ r.X(S4E)(S3B) 


l^(S4EHS^)_ 



js]J)Ts2e')_ 

(SIE) (S2E) 


JS^SB^I^E^ 

(SISEMSOE) 


SECTION 0 
I BORROW 



.CONTROL DATA 
CORPORATION 


COMPUTER DIVISION 


ADDER /SHIFTER 

GROUPS 0 a I 














TO BIT II 

OF SHIFTER MANUAL (BIT 10) 
65-C56-24 I7-D64-N__. 


L 

p53-B53-l 
I ApN_IO_ 
[55-B52-I1 


I _AU2 !P 

53-B53- ZeY^ 

_AUG ± 
53-B53-8 “Y' 

. i 

55-B52-8 
MG_ 9 A I 
53-B53-IO~T^ 
^DN. 9 

‘55-B52-I0 Y* 



ADDER /SHIFTER FANOUT 
BM 

I 


FROM BIT II 
I9l OF SHIFTER 
Y 65-056-12 


£1A LIGHT (BIT 101 \ 

Y I7-A64-2Z 


LIGHT (BITS) 
17- A64-24 



REG 

3 1-048-24 A * 

33-D48-I8 Q ' 

37-A43-I8 P 

39- B49-27 X ) 

4I-A47-I8 Y I 

67- 042-17 MASK 



31- 049-11 
33- 048- 17 
37- A43-I7 

67-042-16 
4I-A47- 17 
39-B49- 18 


/ 

/ / 
/ / 

^ ^ . 
/ / / / 
//// 

/ / / / y 

/ / // /r- 

/ / // / r 

' /// ^ 


_(Sj0EJ(«E]^ 



JS7B)J^S^E)_ 

(S8E)(S7E) 



, MANUAL (BIT 9) 
/ 17-064-15 


V A56 

ni Ivool 


L _Au^ a Is 

P3-A53-24 
1 _ADiJ _8 
p5-A52-24‘y >0 

p5-A52-l9J^ 

T^53-A53- 1 972 


V _AI^ 7 _Xj/5 
p3- A53-4 

I AON _7 

p5-A52-4 

K. —AUG 7 A 1 1 

p3-A53-l2 
K _ADN J 

755- A 52 - 12715 


. MANUAL (BITS) 
' 17-064-17 

BIT 8 


_2lA LIGHT (BIT8) 
T I7-A64-28 


) LIGHT-(BIT 7) 
I7-B64-I3 



31 - 049-23 
33- 048-28 
37- A43-28 


31- 049- 27 
33- 049- 2 
37- A44-2 


ADDER/ rn 
SHIFTER ' 
P. 6 I 

B55*^8( 



[(S6E)£S«)_ 

C S^_ 

[^{S6E)^S^)_ 

US4EM^3B)_ 

1 S4l 


(S^Bj^ZJ) _ 
(S1EHS2E) 


SEOTION I 
I BORROW 


A 

Yze |vio 

BORROW INPUTS 


^SI4B l28 

^SKEHSJ3E2 ^0~ 
JsI2b1_ 

^(‘sjZEMSM^ -(ic^ 

SiOB Art 


(SI0E)(S9B) JI5JE 


SEOTION 0 
I BORROW 


BORROW L 
INPUTS 


, (SI5BHS0E) AzJ^ 


(SI5E)(S0E) I |g 
I p - ^ 


: Y , 

iJS^BJ (S0E2(Sj_5E_)^(S^E^ 


GROUP 0 1 

ADDER/ 20<: 

SHIFTER T 

G55 ,„A 

P. 57 IBC 


SHIFT TO BIT 6 FROM MANUAL(BIT7) 

47-B60-I7 OF SHIFTER BIT 6 OF 17-064-19 


A CONTROL DATA 

TrTLI 

PKOOUCT 

1704 

^ CORPORATION 

ADDER / SHIFTER 



GROUPS 485 

C 60152700 

COMPUTER DIVISION 


■ MIfT »*•! 

Od 




BIT 15 

SHIFTER MANUAL (BIT 14) 
-E55-I2 I7-D64-3 



iiA LIGHT (BIT 14) 
T 17- A64-II 


LIGHT (BIT 13) 
I7-A64-5 


ADDER /SHIFTER FANOUT 
054 


SECTION I 
I BORROW 



33-D48-I Q 
37-A43-I P 

39-B49-I4 X 
41-A47-I Y 
67- D4I- 17 


31- C48 -7 
33- D48-I2 
37- A43 -12 

67-D4I -16 
41- A47- 12 
39 - B49-I3 


^SKB_ 

^ ^(S24Ej(S23BJ ~ 

V. ^{"skeksTseI jfejT' 

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(ITIeTTsTTF) 

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°4°a’’l LX <H°L‘ jiMI 

ADDER/ 

63 Po-* - -Oi? 


^A 27'T^y^ 

I ^ .BORROW INPUTS 


BORROW 

INPUT 


6 





12 ^24 ^26 

\ , manual (BI 

. / 17- 064-5 


C56 

9 IVOOl 



) ^ - 

^ ^ ^ ^ 




^ ^ 

r 


r 

C54 

' I 

|V06 

i: 

rn 

1 ' 


MANUAL (BIT 12) | ' 

/ ~JiX 

17- D64-7 1 

/ ^"1 

BIT 12 ' 1 

Yz7 a 

LIGHT (BIT 12) , 
I7-A64-3 1 ' 

\ ^ 

1 1 

n— 

1 1 
J 1 

1 


LIGHT (BITII) 1 

I7-A64-I8 

— 1 


— 3 1 

BIT II 1 


V. 1 

/L>^ 

's. 


I 

/ . T 


31- C48-22 
33- D48-I I 
37- A43-I I 


67-041- 8 
4 1 - A47 - 1 1 
39- B49-4 


31- C48- 23 
33-048-27 
37- A43- 27 


MANUAL (BIT II) 
I7-D64-9 


SECTION 0 
1 BORROW 


(^EHS^B)_ 1 25 

Ai®I 

(S6E)(S5E) X 20 . f 


GROUPS 

ADI?ER/ rTX*SJEj_IS2B)_ 


GROUP I ° 
ADDER/ 
SHIFTER |( 


rVnI 

-^ 67-042- 26 

1 

1 

1 

1 

L — ; 

- 0 4I-A47-27 

1 

1 

1-- 5 

|— ^ 39- B49-3 

4 

1 

1 

1 

1 


[j_(S_4EJ^(S3E)_ 



^{s1¥hT|T}_ 

^(■s2eTTsTF)_ XJHZ 

-iiL 

jyi5B2(S£Ej^ Js^- 3 K 

(SI5E)(S0E) JL|6 n~ 


GROUP 0 1 

ADDER/ 20 C 
SHIFTER T 


CONTROL DATA 
^ CORPORATION 

COMPUTER DIVISION 

TITLI 

ADDER / SHIFTER 
GROUPS 687 




C 60152700 




J29- A -» 
J08-F5 


J29-B 

J08-F6 


MASK 

REGISTER 


ADDER / SHIFTER , 
59-D54-II ' 


65-D54-I2 Q|7 


INTERRUPT 

REGISTER 


• 71- D38-17 115 
> 55- D52-27 


>71- 038- 4 114 
I 55-052-25 


- T A 

65- 054- 19 Ql 6 


t 71- 038- 2 113 
> 55- 052-23 


J27-A 

J08-FI 

J27-B -»■ 

J08-F2 


J 1 9 - A -» 
J06-FI -»■ 


JI9-B -»• 
J06-F2 


JI7-A 

J06-E7 

JI7-B 

J06-E8 -^>- 


J24-A -» 

J08-E5 -» 

J24-B -» 

J08-E6 ^>- 

J23-A -» 

J08-E3 -» 

J23-B -» 

J08-E4 -» 

J22-A -» 

J06-F7 

J22- B -^y 

J06-F8 ~^y 




— 

EI6 


|V36 

Ls 


— 1 

y>l6 




^8 

^22 

A 

trzA 




^12 
Y 6 

A 

I ® 


|x3 



A 

1 ® 
■k 1 1 


TlI5 

A 

Jm7 



I NOT USEO 
>71- 038-1 112 

> 55-C52-I7 


3 - E46- 4 ( 
ADDER-*- MASK 7 I - D39- 25 ( 
ENABLE INT 69 - 040-4 ( 

3 - E46-I7 ( 
I CLEAR MASK . 

I 15- C36-24 


BIT II Y 

65-C54- I I 026 


63-A54-II 0 26 


-?^'A 

61 - A54-I2 QI7 


A 'V - 


A ZrX BIT 3 

Y 71-044-23 


V A 

61 - A54-I9 0 16 


FROM 

ADDER / SHIFTER 
61 - B54-I8 


too 

3 - E46-7 
ADDER -*> MASK 


A 4A bit I 
^ Y 75-B34-26 


tso 

3 - E46- 19 


Y 


B 

1 \ D 1 

A ^ 

- X \ ,1 * 


1 1 


^ 12 

1 

H ] 






3 

Y^ 


128^^ 





INTERRUPT 

REGISTER 1 

A 22 0 7 1- 037-1 I 107 
240 55-A52-27 


180 71- 037-10 106 
^200 55-A52-25 

140 71 - 037-7 105 
^ lOO 55-A52-23 

) ^ NOT USED 

1— ^ 71 - 037-18 104 


MASK INTERRUPT 

REGISTER REGISTER 1 

Z3 A 226 71- 038-23 HI 


BIT 10 A 

63-B54-I2 Q|7 


bits ^ a 

63- B54-I9 016 


BIT 8 

63- A54-I8 < 


3- E46-6 C 
ADOER-*'MASK 7i-D39-26L 
ENABLE INT 69- 040-12 L 
3- E46-I8 i 
CLEAR MASK IS- C36-26C 


24p 55-C52- 27 


A 180 71- 038-26 HO 
206 55-B52-25 


A 140 71-038 - 25 109 
^ lOQ 55- 852-23 


I NOT USED 
I 7l- 038- 28 roe 
> 55-A52-I7 


note: 

L SEE PAGE 71 FOR BASIC INTERRUPTS. 
2. J= JACK. 


A CONTROL DATA 7704 

m CORPORATION OPTIONAL MASK, „i, i . ;o THT 

INTERRUPT REGISTERS, c 60152700 U 

COMPUTER DIVISION AND RECEIVERS i MKTjT;.. -J 



PROGRAM PROTECT 


Module V54 contains three FFs which control program protect and protect 
violations. The Instruction Protected FF retains the state of the previous 
instruction. If the FF is set, the previous instruction was protected. If 
the FF is clear, the previous instruction was not protected. An interrupt 
occurring during the B cycle also sets the Instruction Protected FF. This 
simulates a protected operation while writing a return address. 

Whenever a violation of the program protect system is detected, the Protect 
Fault FF sets and an internal interrupt is enabled. A 00 interrupt occurs if 
mask bit 00 is set and the interrupt system is active. A violation indicates that 
the nonprotected program has attempted an operation which could harm the pro- 
tected program. The four program protect violations and their setting inputs to 


the Protect Fault FF are: 

Violation Input 

1. A nonprotected instruction attempts to write into a storage from 

location containing a protected instruction/operand. The pin 20 

contents of the storage location are not changed. 

2. An attempt is made to write into a protected storage location from 
via the external storage access when a nonprotected instruc- pin 20 
tion was the ultimate source of the attempt. The contents of 

the storage location are not changed. 

3. An attempt is made to execute a protected instruction fol- from 

lowing execution of a nonprotected instruction. The inverter J 


protected instruction is executed as a nonprotected Selec- 
tive Stop instruction. It is not a violation, however, if an 
interrupt caused this sequence of instructions. 

4. An attempt is made to execute the following instructions from 

when they are not protected: Interregister with bit 0=1, inverter=^ 

EIN, IIN, EXI, SPB, or CPB. These instructions become 
nonprotected Selective Stop instruction under these circum- 
stances. 

The FF at the bottom of module V54 sets when violation number 3 is present. 
The output of this FF blocks the setting of the ADR FF and sets the REG FF in 
the Sequence controls. Therefore, if either violation 3 or 4 is present and REG 
mode selected, the F register clears. The computer recognizes the 00 code in 
the F register as a Selective Stop instruction. If the Selective Stop switch is in 
the stop position, the computer stops. If the switch is in the neutral position 
the instruction is executed as a nonprotected pass instruction. A "0" output at 
pin 6 clears the upper portion of the X register. 


INTERRUPT 


All three FFs on module V59 must be set for the computer to process an interrupt. 
The order of events for enabling the interrupt system is as follows: 

1) Set first Enable Interrupt FF 

2) Set second Enable Interrupt FF (interrupt system active) 

3) Set Interrupt registers 

4) Interrupt priority is checked 

5) Interrupt FF is set (there is an interrupt) 

The first Enable Interrupt FF is set at time 250 of the B cycle during REG of an 
Enable Interrupt or Exit Interrupt instru ction. Th e second Enable Interrupt FF 
sets at time 200 of the B cycle when the ADR (ind) condition is present and the 
first Enable Interrupt FF is set. For the Enable Interrupt instruction, this 
delay allows one more instruction to be executed before enabling the interrupt 
system. There is no delay when using the Exit Interrupt instruction. 

At time 50 of the A cycle, the second Enable Interrupt FF sets the Interrupt 
register, providing the Interrupt FF is cleared. The Interrupt FF must be 
cleared to insure that an interrupt is not in process at the same time the Interrupt 
register is being set. 

At time 250 of the A cycle, the Interrupt FF sets if all of the following conditions 
are present: 

1) The second Enable Interrupt FF set 

2) Interrupt signal present from interrupt priority 

3) ADR (ind) + RNI 

The interrupt occurs reading an instruction from storage or reading an 
indirect address. 

Two main gates clear all three FFs and disable the interrupt system. The 
first gate clears all three FFs when an interrupt state is entered and the 
following conditions exist: 

1) A cycle 3) ADR (ind) 

2) time 300 4) RNI 

This gate disables interrupt while the computer stores the registers and sets 
the new mask. The second gate clears the FFs and disables interrupt when 
the following conditions exist: 

1) A cycle 3) REG (ITN) 

2) time 200 

This gate disables interrupt while the computer restores the registers in 
preparation of exiting from an interrupt state. 


S8 

Rev. A 



04 0 
Iv59l 


B36 
|V06 
I NT 




notes: 

© DENOTE PAGE NUMBER FROM LOW SPEED COMPUTER DIAGRAMS. 



3L CONTROL DATA 

TITI.I 

PROGRAM PROTECT 

MOBUCr 

1704 



• IZI 





COMPUTER DIVISION 

AND INTERRUPT 

c 

60152700 

“L 




• MIT 

69 



MASK REGISTER AND INTERRUPT PRIORITY 


The basic 1700 Computer has two interrupts. They are as follows: 

1) Interrupt state 00 = (internal) Storage Parity Error or 
Program Protect Fault 

2) Interrupt state 01 = (external) Low- Speed I/O 

An option may be added which gives an additional 14 external interrupt lines. 
Thus, the computer may have 16 different interrupts. The discussions that 
follow assume the computer has 16 interrupts. 


BAStC 

INTERRUPT 



TERNAL INTERRUPT 
LINES (ADDS 14 INTER- 
RUPTS ) 


instruction from that particular interrupt state. For example, if the priority 
input comes from Interrupt register bit 07, then the output code is a binary 0111 
The first three columns in Table 1 show the relationship between interrupt 
states, A portion of EXI instruction, and location of the return address. When 
an interrupt state is recognized, the. A portion of the EXI instruction is formed. 
Delta defines the interrupt state from which the exit is taken. The EXI instruc- 
tion automatically reads the address containing’ the return address and jumps to 
the return address. 


BIT 

07 


PRIORITY 

CODE 

A 

/ V 


BIT 

00 


0 0 01 110 0 


A PORTION OF EXI INSTRUCTION 


I C 

If two or more interrupts have equal priority and occur at the same time, 
computer recognizes the lowest interrupt line. For example, if interrupt 
states 05 and 12 occur at the same time, the priority network recognizes 
interrupt 05 and forms a binary output code of 0101. 


the 


The interrupt state priority code output transfers to the Y register via the 
■V22 module on page 41. 

TABLE I. INTERRUPT STATE DEFINITIONS 


MASK REGISTER 

The 16-bit Mask register is the enable for each interrupt state or line. Bit 00 
of the Mask register corresponds to interrupt line 0, bit 01 to line 1, etc. To 
enable an interrupt line, its corresponding bit in the Mask register must be 
set. The Mask register is set by the Inter- Register instruction. 

Module V09 shows the first 4 bits of the Mask register and Interrupt register. 
Three additional V09 modules are added if 16 interrupts are used. The Mask 
register is set by the Adder -* Mask Control FF on module 'V‘44. The output of 
the Mask register returns to the Adder /Shifter, 

ADDER - MASK CONTROL 

The Adder -►Mask FF has two main setting gates. The first gate is satisfied 
if the manual Mask register selector on the console is activated and the Q -► 
Adder FF is set. At time 'V’250 of the A cycle, the second gate is enabled if 
(REG) (IR) (Xj.) = 1. Xq (X register, bit 0) indicates that the Mask register 
is the destination register during an Inter- Register instruction. The Mask 
register sets at time 300 according to its selected Adder/Shifter inputs if the 
Adder -► Mask FF is set. 

INTERRUPT REGISTER 

The 16-bit Interrupt register is a holding register for the 16 interrupt lines 
and sets if all of the following conditions are present: 

1) The corresponding bit in the Mask register must be set. 

2) The corresponding interrupt line signal present. 

3) The Enable Interrupt FF set (by an EXI + EIN instruction) ,t50 
(A cycle), and INT FF clear. 

INTERRUPT PRIORITY 

The interrupt priority consists of modules VI 1 and VI 2. When one of the 
Interrupt register bits sets, the priority network recognizes which interrupt 
line is present and forms a 4-bit code. The code specifies A for the Exit 


Interrupt 

State 

Value of 
A to 

Exit State^^g 

Location of 
Return Address 

Location of 
First Instruction 
After Interrupt Occurs^ g 

- 

"oo 

00 

0100 

0101 

1 

Loi 

04 

0104 

0105 


"02 

08 

0108 

0109 


03 

OC 

01 OG 

01 OD 


04 

10 

0110 

0111 


05 

14 

0114 

0115 


06 

18 

0118 

0119 


07 

1C 

one 

OllD 

❖ < 

08 

20 

0120 

0121 


09 

24 

0124 

0125 


10 

28 

0128 

0129 


11 

2C 

01 2C 

01 2D 


12 

30 

0130 

0131 


13 

34 

0134 

0135 


14 

38 

0138 

0139 


.15 

3C 

01 3C 

013D 


Interrupts in basic computer 

'^‘interrupts added by 1705 Interrupt/ Data 70 

Channel option Rev. A 






BIT 3 

EXTERNAL INTERRUPT 
67 -DOB - 20 


FROM 

ADDER/ SHIFTER 
61- B54 - I I 


BIT 2 

EXTERNAL INTERRUPT 
67- DOB- 8 


BIT 2 
59- C54-I2 


INT BIT I 
75- B34-27 


BIT I 
59- C54-I9 


D39 



note; 

SEE PAGE 67 FOR ADDITIONAL 
INTERRUPT LEVELS (1705 OPTION). 



“I 


J 


, CONTROL DATA 
CORPORATION 


MASK REGISTER AND 
INTERRUPT PRIORITY 


170 ^ 


60152700 


■ NitTiMtt . 


COMPUTER DIVISION 



SHIFT, MUI, AND DVI CONTROLS 


The V72 module contains the logic that controls the shift instruc- 
tions. Shift instructions are identified by a zero instruction field (F) and 
a hexidecimal F in the sub-instruction field (F^) Bit positions X05-07 
identify the type of shift instruction. Below is the format for the shift 
instructions. 


15 12 II 8 7 6 5 4 0 

F F' 


0 0 0 0 

1 1 I 1 

n 

□ 

□ 


1 = SHIFT LEFT } ' 

0= SHIFT RIGHT 

|s SHIFT A 

1 = SHIFT Q 


' ' V ' 

SHIFT COUNT 


The Shift Cycle FF controls the shifting required by the shift 
instructions. The first shift occurs during the A cycle and the remaining 
shifts occur during the C cycle. At time 250 of the A cycle, the shift 
count (currently in bit positions XOO-04) is sensed for a count of zero. If 
the shift count is zero, the Shift Cycle FF is not enabled and the logic 
proceeds to B cycle RNI, If the shift count is not zero, the Shift Cycle 
FF is set and a shift occurs. The shift count then replaces the lower 5 
bits of the Y register and is decremented by one. The Y register now 
contains the shift count. 

At time 250 of each pass of the C cycle, a shift occurs and the shift 
count decrements by one. The logic proceeds to B cycle RNI when the shift 
count decrements to zero and at time 250 of the C cycle. 


The SRI and SR2 FFs on the V65 modules sense the sign of the 
operands used in Multiply and Divide operations and determine the sign of 
the result. Any negative operand must be complemented because the 
associated logic recognizes only positive numbers. The two SR FFs 
record the complemented operands. 

The SR2 FF senses the signs of the operand in the Multiply or 
Divide operations and becomes enabled if it is negative and the correspond- 
ing conditions are met. The SRI FF senses the sign of the operand in the 
X register and becomes enabled if it is negative and the corresponding 
conditions are met. The output from pin 26 goes to the Adder controls 
and enables the complementing of the negative operand. 

Note that the SRI FF senses the sign during Multiply operations 
and the SRI and SR2 FFs sense the sign during Divide operations. The 
SRI FF senses the sign of the quotient and the SR2 FF senses the sign of 
the remainder. The remainder maintains the sign of the dividend. 

The output of pins 1 and 3 of the V63 module control the comple- 
menting of the product, quotient, and remainder. The condition Y00-04=0 
signifies that shifting is completed (MUI or DVI instruction is finished) and 
the result is ready to be complemented if it is negative. 

A Multiply instruction multiplies the contents of the storage location 
specified by the effective address by the contents of the A register. The 
32 -bit product replaces the contents of Q and A with the most significant 
bits in the Q register. Bit Q15 is the sign bit. 

The lower 5 bits of the Y register hold the shift count that is set to 
10^ g at the start of each Multiply instruction. The shift count is decre- 
mented by one before each shift operation. 

The Adder/ Shifter can shift a maximum of bits (one register 

at a time). It is therefore necessary to have a bit bucket to hold the lowest 
order bit of the Q register during a shift that impliments both the A and Q 
registers (32 bits). During a Multiply instruction, the contents of QA are 
shifted right, end off, one place. The lowest order bit of the Q register is 
placed in the bit bucket and the contents of the Q register are right shifted 
one place. The contents of the A register are then right shifted one place 


72.0 
Rev. A 




SHIFT, MUI AND DVI CONTROLS (Cont'd) 


with the contents of the bit bucket replacing bit position A^g. A more 
detailed description of the bit bucket logic is on page 56, 1, 

The Multiply bit (MB) is in bit position AGO during the first shift 
operation (A cycle) and is in bit position Aq^ during the remaining 15 ^q 
shift operations (C cycle). If MB=0, the contents of QA are right shifted 
in as previously described. If MB=1, the contents of the X register (stor- 
age location specified by the effective address) are added to the contents 
of the Q register and the sum replaces the contents of the Q register. The 
contents of QA are then right shifted as previously described. 

Below is an example of how the Multiply instruction operates. 


Example: 


Q 


(A) = 1FA2 
(X) = 

(A)(X) = 9E2A 


16 


ooooooooooooooooi 

000 

010 

001 

000 

ooo| 

010 

001 

oil 

100 

100 

100 

100 

100 

010 

001 

000 


000111111010001 ^ 
OOOOllllllOlOOQJ, 
lOOOOllllllOlOQ^I^Q 
0100001111110100 
1010000111111010 
0101000011111101 
1010100001111110 
0101010000111111 
0010101000011111 
0000010100001111 
1000101010000111 
1100010101000011 
1110001010100001 
1111000101010000 
0111100010101000 
0011110001010100 
1001111000101010 


MB 


Bit 

Bucket 


ex: MB=1 
(Q) = 000 
(X)=101 

J^\ 

{Q)-^ Bit 


Bucket 


ex: MB=1 
(Q)=001 
(X)=101 


(Q)- 


Bit 

Bucket 


1001111000101010^= 9E2A,^ 
4 Id 


During a Divide instruction the contents of the effective address (X 
register) is compared with the contents of the Q register. If (X) > (Q) a 
"1" enters EAB (End Around Borrow) and a "O" enters the bit bucket. A 
Long Left Shift shifts QA one place with the "0" in the bit bucket replacing 
bit position AOO, Note that the bit bucket always contains the complement 
of the state of the EAB. 

If (X) < (Q) a "0" enters EAB and a "l" enters the bit bucket. The 
contents of the X register is subtracted from the contents of the Q register 
and the difference enters the Q register. A Long Left Shift shifts QA one 
place with the "l" in the bit bucket replacing bit position AOO. In a QA 
shift, the Q and A registers are shifted separately since a maximum of 16 
bits can be shifted at one time. Bit A15 replaces bit QOO through the 
associated logic of the Adder/ Shifter. A more detailed discussion of 
the logic of this process is on page 58. 6. 

This comparing and shifting process continues until the shift count 
reduces to zero. The shift count in the Y register operates the same as 
in the previously described Multiply instruction. 


72. 1 
Rev. A 




SHIFT, MUI AND DVI CONTROLS (Cont'd) 


The Divide instruction divides the contents of Q and A registers with 
the contents of the effective address. The Q register contains the most 
significant bits before execution. The quotient is in the A register and the 
remainder in the Q register at the end of the Divide operation. 

Below is an example of a Divide instruction. 


Divide: 


(A) 

(X) 1 (QA) 


Q = 0 
A = 272E 


X = 2 


36 


16 


0010011100101110 „ 


Y EAB 


0000000000000000 

0010011100101110 

F 



000 



1 

0 


0100111001011100 

E 



000 



1 

0 


1001110010111000 

D 



001 



1 

0 


0011100101110000 

c 



010 



0 

1 

000 

0111001011100001 

B 



000 



1 

0 


1110010111000010 

A 



001 



1 

0 


1100101110000100 

9 



oil 



0 

1 

001 

1001011100001001 

8 



oil 



0 

1 

001 

0010111000010011 

7 



010 



0 

1 

000 

0101110000100111 

6 



000 



1 

0 


1011100001001110 

5 



001 



1 

0 


0111000010011100 

4 



010 



0 

1 

000 

1110000100111001 

3 



001 



1 

0 


1100001001110010 

2 



on 



0 

1 

001 

1000010011100101 

1 



on 



0 

1 

001 

eoooiooniooion 

0 



010 



0 

1 

000 

0001001110010111 





Bit Bucket 


ex: Q > X 
EAB = 0 
Bit Bucket = 1 

(Q) = 010 

(X) = " 010 
000 

Replaces (Q) 


Remainder 


Answer 


The V73 module contains the Multiply Step, Multiply Bit, and Divide 
Step FFs. These three FFs enable the logic that controls the Multiply and 
Divide instructions. 

The Multiply Bit FF senses bit location AOO during the A cycle 
and bit location AOl during the C cycle. If the sensed bit is a "l" and the 
corresponding conditions are present, the Multiply Bit FF sets and enables 
the logic that performs the adding of (Q) and (X) as previously described 
in the description of the multiply procedure. 

The Multiply Step FF sets on the condition (MUI) (ROP) (050) 
(Y00“04jt0) (C cycle). The Multiply Step FF enables the shifting and 
associated logic that performs a Multiply instruction. The Divide Step 
FF enables the shifting and associated logic that performs a Divide instruc- 
tion. 


72.2 
Rev. A 




,24l (SHIFT CYCLE) Q 
5> - C59- 15 


t60 3- C6I - 17 


C CYCLE 
II- E53-27 Y 

(Y00-04=0)(QA)Ai5 

HOO 3- C6I - 18 
HOO 7- A59- 21 

Y00-04=0 /V^ 
43-A39-II T9 


< (A + Q) 

3-l0jSHI^T 


SHIFT CYCLE (A)(Q) 
I 49-A59-5 

I Zsj SHIFT CYCLE 
I y 5 I - D59 -19 

_23lsHIFT CYCLE (A) 

19 JL SHIFT CYCLE (T) 

Y “ C59 -7 

SHIFT CYCLE 

Y ^9- 959- 28 


MUX 

27-050 -3 


AI5 = I 
43-035 -17 


(ROP) EOR 
29- A57- 15 


XI5= I 

39-B42-20 


X6 39-B44-l5( 


. QA SHIFT 
' 41 - A4I-I4 


B CYCLE 
II- ESI -26 ' 


t50 3-C6I-I9 


OlV, STEP 
73- A6I-5 


(SHIFT CYCL E) 

3 I (MULT. STEP)(DIV. STEP) 

Q 49- B59-27 

— kj 51- 059-16 


A CYCLE 
II- E52-25 


(ROP)(MUI + DVD A6 . 
27-050-15 


i (ROP) ( MUI+ DVD+ 

SHIFT CYCLE 
M - E53-I6 

(ROP)(MUI+ OVD + QA SHIFT 
57- E55- 27 


ROP I 9 - C49 - 7 


note: 

062 MAY BE A V72 MOOULE IN SOME MACHINES. 
IF SO, SEE LOGIC SCHEMATICS. 


_tA(OVI)(SR 2) 
r 45- C63-I3 


Y00-04S 0 
43-A39- 7 


MULTIPLY 

STEP 


J 73-062- 2 
) 29- A57- 6 
) N U 


(MUX 4- OVI) (ADR)(SR 2)-f (ROP) 
)(EOR)+(MUX+ OVI)(ROP)(SR I) 
45-C63-7 


SHIFT 
29- C5I - I 
A CYCLE 
II- E52-28 

AOO = l 
35-C44- IB 
AOI = l 

35-C44-I I 


I 26A shift + MULT. STEP 
I Y 51- 059-18 


EXI (ROP) . 
29- C5I-2I ' 
MUI (ROP) . 
27 - 050-12 ' 

C CYCLE f 
I I - E53-26 ' 


) [mUI (MB = D + EXl]] ROP 
49- B59-5 


J£A0IV. STEP + MULT, STEP 
T49-B59-9 (MB=I) 


(ROP) OVI 
27-050-0 


OVI (Y00-04 = 0) 
)(SR 2) + MUI. (SRI) 
45- C63-2I 


H02 

7- B58-28 Y ^ 
♦50 

3-C6I-20 

HOO JL ^ 

7-A59-25 

too 

3-B62-4 

H03 

7-A38-4 Y^ 


CONTROL DATA 
m CORPORATION 

COMPUTER DIVISION 

TITLl 

SHIFT, MUI, a DVI 
CONTROLS 




1 






AQ I/O 


The AQ I/O Channel operates in such a way that the Q register of 
the computer contains the address of the peripheral device and the data 
transfer occurs to/from the A register of the computer. 

INPUT ON AQ CHANNEL 

A single word transfers to the A register whenever the computer 
executes the Input to A instruction (QOO-0). The request for data by the 
computer is signified by a "1" signal on the Read line. The peripheral 
device whose address is in the Q register responds with a Reply when data 
is available to the A register. 

If no data is available the peripheral device responds with a Reject. 
In either case the peripheral device must respond with a Reject or Reply 
within 4 microseconds. If no response is obtained in 6 microseconds the 
computer generates an internal Reject. Reply causes the computer to go 
to address P + 1. (P is the address of the input instruction). Internal 
Reject causes the computer to go to address P + A, where A is the lowest 
8 bits of the input instruction, the highest of which is a sign bit. External 
Reject causes the computer to go to address P + 1 + A. 

OUTPUT ON AQ CHANNEL 


The Read or Write signals enable transmitter circuits on the ZT 
module, a 7 usee delay on the V88 module,and a signal at pin 24 of the 
V74 module. The "O" output at pin 24 enables the computer timing chain 
when the following condition is present: 

{Read + Write ) (Re ply Reject) 

The Reply or Reject signals enter receiver circuits on a ZS module 
(location D20). These signals then set the appropriate FFs on module V74, 
If neither a Reject or Reply signal is received within 7 usee, an internal 
Reject is generated and the Reject FF sets. 

The Character Input signal is received on a ZS module (location 
D12). This is a "l" signal sent to the computer during Input operations. 

If this signal is present during an Input to A the lower 8-bit character is 
loaded into the lower 8 bits of A without disturbing the upper 8 bits of A. 

EXTERNAL INTERRUPT 

Pins 26 and 28 of module V74 are external interrupt lines. These 
interrupts are OR'ed together in forming interrupt 01. The following 
figure shows the interrupt system including the 1705 option. 


The output on AQ operates similar to Input on AQ. The presence 
of the output data is signified by the presence of a '*1" on the Write line. 
The responses are identical for input and output. 

LOGIC FOR AQ I/O 

Module V53 contains the Read FF for Input instructions and Write 
FF for output instructions. The "O" signal at pin 27 disables the computer 
timing chain when an Input or Output instruction is recognized. 


BASIC 

INTERRUPT 



15 ADDITIONAL EXTERNAL 
INTERRUPT LINES (ADDS 14 INTERRUPTS) 


74 

Rev. A 



REG (INP) 
25- B5I- 5 


V200 l/e 

7 - A58- 23 

REG (OUT) 
25-B5I-I T 


REG(INP+OUT) . 
25-B5I-3 


A CYCLE . 
I I-E52-24 


BIT 15 
97-B28-27 
FROM i REG 


012-15*0 35-D45-23 


QllsO 33-048-23 



3-BI7-8 0 


1 

■ |V53| 

i 2 



1 1 r 

V 


A 

\ ° 4^® 

/e 



CD 

75-D20-I8 


3-BI7-2 0 

■read" +“wmTE 


INSTRUCTION PROTECTED ! 27 
69-A45- ISS^^ 


I {REG)(INP)+ (OUTMA) 
D 3-817-28 0 


SEE P. 43 
AND BELOW 


j7/iSEC DELAY 
^ SEE P. 19 



t50 3-C26-9 



I9-B36-I5 

DI4-X 


0 3-BI6-2I REJECT 

REJECT 



0 5-BI5-20 




D34 

k 


|v»3 



SEE 

p. 43 

L 

AND 

ABOVE 


97-B28-IB 
BIT 15 TO 2 REG 
I NU 


- ^ ^ 3-BI6-28 REPLY 
" ^ REPLY 


1.2V 75-B34-7 
t25 3-C25 - 19 

V2S0 7-B40-27 

EXTERNAL INT. . 

BIT I ^ 67-EI7-4 

0 9-BI2-I5 

INTERRUPT 


J03 - F7 

22Vl 

J04-F7 
J03 - F8 
J04 - F8 


J03-D9 
J04-D9 
Y2jn->>— J03-DI0 
J04-DI0 



^>- JOT - El 
^>— JOS - E I 
►>— J07-E2 
>->— JOS - E2 



) (REPLY + REJECT) 
I 7- B38-22 


REJECT 

43-D34-24 


2M INTERNAL REJECT 
— Q 19- A63-22 


27 J INT BIT 01 
— KJ 7 i_ D44-7 


notes: 

0 DENOTES PAGE NUMBER FROM 
LOW SPEED COMPUTER DIAGRAMS. 


ifc CONTROL DATA 
m CORPORATION 

COMPUTER DIVISION 

TITLt 

AQ I/O 
PART 1 









TABLE 2. ZS MODULE CABLING 


Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

D12 

3 

J06-D2 

D15 

3 

J02-D2 

D16 

3 

J02-C6 

D17 

3 

J02-B10 


5 

J05-D2 


5 

J01-D2 


5 

J01-C6 


5 

JOI-BIO 


6 

J05-D1 


6 

JOl-Dl 


6 

J01-C5 


6 

J01-B9 


8 

J06-D1 


8 

J02-D1 


8 

J02-C5 


8 

J02-B9 


13 

J02-D8 


13 

J02-C10 


13 

J02-C4 


13 

J02-B8 


14 

J02-D7 


14 

J02-C9 


14 

J02-C3 


14 

J02-B7 


15 

J01-D8 


15 

JOI-CIO 


15 

J01-C4 


15 

J01-B8 


16 

J01-D7 


16 

J01-C9 


16 

J01-C3 


16 

J01-B7 


21 



21 

J02-C7 


21 

J02-C1 


21 

J02-B5 


23 



23 

J01-C7 


23 

JOl-Cl 


23 

J01-B5 


25 



25 

J02-C8 


25 

J02-C2 


25 

J02-B6 


27 



27 

J01-C8 


27 

J01-C2 


27 

J01-B6 


Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

D18 

3 

J02-B4 

D19 

3 

J02-A8 

D20 

3 

J02-A2 


5 

J01-B4 


5 

J01-A8 


5 

J01-A2 


6 

J01-B3 


6 

J01-A7 


6 

JOl-Al 


8 

J02-B3 


8 

J02-A7 


8 

J02-A1 


13 

J02-B2 


13 

J02-A6 


13 

J02-D6 


14 

J02-B1 


14 

J02-A5 


14 

J02-D5 


15 

J01-B2 


15 

J01-A6 


15 

J01-D6 


16 

JOl-Bl 


16 

J01-A5 


16 

J01-D5 


21 

J02-A9 


21 

J02-A3 


21 

J02-D3 


23 

J01*-A9 


23 

J01-A3 


23 

J01-D3 


25 

J02-A10 


25 

J02-A4 


25 

J02-D4 


27 

JOI-AIO 


27 

J01-A4 


27 

J01-D4 





Q REGISTER 


35- D45- 16 CX^ 
EI 8 -X (T 25 


\Z 

35- D45-I2 



►>— J04-DI 
►>— J03 - D I 
►>— J03-D2 
►>— J04-D2 

►>— JOS- C9 
►>— J04-C9 
►>— J03-CI0 
— J04-CI0 

J03-C7 
►>— J04-C7 
►>— J03-C8 
►>— J04-C8 

►>— J03-C5 
»— J04-C5 
►>— J03- C6 
►>— J04- C6 


BIT II 

35-D46-I7 


35 - 046 - 26 



»— J04-C3 
►>— J03 - C3 
X>— J03-C4 
J04- C4 

J03-CI 
»— J04-CI 
►>— JOS - C2 
►>— J04 - C2 

►>— J03- B9 
►>— J04 - B9 
>y- J03 - BIO 
J04 - BIO 

►>— J03- B7 
J04-B7 
»— JOS - B8 
►>— J04- B8 


BIT 07 

35- 046-7 


35- 047- 17 0 27 


35- 047-12 Q I® 


J03- B3 
A 8y~^>— J04-B3 
^ J03-B4 

J04- B4 

J03-BI 
A 23y-^^— J04- Bl 
^24^>_ J03-B2 
26Y^>— J04- B2 
^ yO-»— JOS - A9 
A 22Y-»— J04- A9 
^ JOS - AlO 


BIT 03 I 

35-047-26 C 


00 I 

35-047-22 6 I® 


JOS - A5 
8t>»— J04 - A5 
^ J03- A6 

J04- A6 

J03 - AS 
230-»— J 04 - A3 
^ 24j^>— J03- A4 
ZSWy- J04-A4 

J03- Al 
22y-^>— J04-AI 
^ J03-A2 

, >Q-»— J04 - A2 


A REGISTER 




NU 35-042-26 0^^ 35-043-17 

I 9031-048-21 


MU 35-042-12 6 '^^ A 35 - 043-11 

1 1 O 3 1 - 048 - 28 


35-042-17 ^25 


07 

35-043-18 


9031- 048-27 



31-050-8 



NU 

31-050-21 

D 20 


BIT 

00 

NU 35-044-22C 

31-050-28 

[i!_ 

A'°c 

9 e 

)NU 

)3!-C50-Z7 

READ . 

'1 75-034-12 ^ 

)I 8 20 c 

SEE R 75 

)- T 
1 


A control data 

m CORPORATION j/q 

COMPUTER DIVISION 2 












S TOE AGE 






1700 STORAGE 


GENERAL INFORMATION 

The 1700 storage consists of up to eight banks of magnetic core storage. Each 
bank contains 4096 locations for 18 -bit words. The format of the storage words 
is shown below. 


17 16 15 0 


ST- 
OAT A 

PARITY BIT 

PROGRAM PROTECT BIT 


The circuits for the eight banks are identical. The storage timing and control 
circuits select the storage bank from the translation of the three high-order stages 
of the address (S register). 

The description of the storage circuits is based on bank 0 which is provided with 
the basic system. Unless otherwise stated, the description of the bank 0 storage 
circuits applies to the banks contained in any of the 1700 storage options. 

Each storage bank consists of the storage stack, inhibit decks, and drive decks. 

The storage stack contains 18 planes of magnetic cores assembled in the conven- 
tional matrix arrangement. 

Current-carrying -wires pass through the cores and magnetize them in one direction 
or the other. The direction of current flow determines the direction of magnetization. 
Approximately 400 ma^urns of magnetizing force are needed to switch a core into 
one of its two stable states ("l" or ”0"). 

Five wires pass through each core. They are: 

• A horizontal drive (x wire) 

• A vertical drive (y wire) 

• A horizontal inhibit (Ixwire) 

• A vertical inhibit (ly wire) 

• A diagonal sense (S wire) 

Coincident currents (one x and one y) switch the cores. A core is addressed by 
simultaneously transmitting half -amplitude (200-ma) current pulses through a 
selected x wire and a selected y wire. 

Only the core at the intersection of the selected x and y wires receives sufficient 
magnetizing current to switch its state. All other cores in the same row or column 
as the selected core receive half-amplitude current pulses which are not sufficient 
to switch the core. In Figure 11, if the left-most y wire and the top x wire carry 
current pulses, core A switches; cores B and C receive half-amplitude currents; 
and core D receives no current pulses. 

The polarity of the residual magnetization determines the binary information in a 
core. The read current pulse on the selected x or y wire stores a"0". The write 
pulse without a coincident current on the I wires stores a **1" in the core. 



Figure 11. Portion of Magnetic Core Matrix 

Applying a read pulse to the selected x and y wires reads information from the 
selected core. If the core previously stored a "l", the pulse switches the core to 
a "O". This change induces a pulse on the S wire. The pulse on the S wire is in- 
terpreted as a "I'^bit from the core. If the core previously stored a "O", the read 
pulse does not affect it. Thus, no pulse is induced on the S wire. 

One memory plane contains 4096 cores in a 64-by-64 array. Each bit of a word is 
stored in a separate plane. Thus, the stack contains 18 planes. 


MAGNETIC CORES 

The magnetic cores used in the 1700 storage planes have two stable magnetic states 
C'l" and "O") because of the square hysteresis loop properties of the ferrite material. 
A current sufficient to cause enough flux density switches the core to positive or 
negative saturation when applied to the selected x and y wires. When the current is 
removed, the flux density drops to the residual positive or negative state. The 
positive residual state corresponds to a "O” and the negative to a "l". 

If a core receives only a half -amplitude current, the core does not switch but re- 
mains in the residual state caused by the last coincident half -amplitude pulses. 


78.1 
Rev. A 





1700 STORAGE (Cont'd) 


Any change in the magnetic state of a core causes a change in the total flux linking 
the core and any winding passing through it. Such a change produces a voltage on 
the sense winding. During the time read current is applied, the output voltage is 
sampled to determine if the core switches. If a large voltage is sensed, the core 
was in the *'l" state. If a small voltage is detected, the core was in the "O" state 
and merely shifted from the positive residual state to the positive saturation state 
and back. 

A common sense line threads through all 4096 cores in a storage plane. When 
reading, 64 x and 64 y eor.es contribute to the sense voltage. The total voltage 
induced by the 126 partially selected cores is less than the voltage induced on the 
line by the one selected core switching from a "l”. The sense line passes diago- 
nally through the cores in such a way that voltages from unselected cores tend to 
cancel. 


STORAGE PLANES 

A storage plane is a 4-by-4-inch printed circuit board which holds 4096 cores in a 
64-by-64 matrix. Five wires pass through each core. Figure 12 shows a simplified 
storage plane containing a 24-by-24 matrix; however, all the principles of this 
matrix apply to the larger matrix. 

The wires that suspend the cores terminate on the inside edges of the board, and 
printed wiring carries the connections to the outside edges (top and bottom) for 
easier access. The 64 horizontal x drive lines are brought to connections on each 
of the two opposite edges of the board. In plane 0, which is used as an example in 
Figure 12 the even-numbered drive lines enter the plane from the DC edge and the 
odd-numbered lines from the AB edge. The letters at the corners of the plane in 
Figure 12fix the reference points of the plane in respect to the two views of the 
stack on the block diagram. The 64 vertical y drive lines enter the plane on the 
other edges in a similar manner. The sense line is a single line threading all the 
cores as shown in Figure 12, The two ends of the sense line terminate at one 
corner of the plane. Inhibit line connections enter the stack on the other three 
corners. 

The inhibit lines are arranged in four vertical and four horizontal stripes or 
quadrants. Thus, the vertical inhibit lines run parallel to the y drive lines and the 
horizontal parallel to the x drive lines. The inhibit drive line for each stripe runs 
through 16 rows or columns of cores. During the write cycle of storage, one 
horizontal and one vertical inhibit stripe is energized coincident with the write 
drive. Thus, one.l6-by-16 area of cores receives full inhibit drive in each plane 
that corresponds to a "O" in the Z register. The cores that receive full inhibit 
drive are prevented from switching to a "l". Since the read drive pulse preceded 
the write and switched the reference core to a "O'*, the full inhibit drive maintains 
the referenced core at the "o” state if the corresponding bit position of the word to 
be restored is a "O". 

The direction of inhibit current in the energized stripes is opposite to the x or y 
drive current of the write pulse, thus preventing the magnetization of the referenced 
core to the "l" state. For example, if write drive current enters the plane on 
lines yO and xO (Figure 12)and a ''O" is to be stored in the plane, the 0 vertical and 
horizontal inhibit stripes are energized with current in the opposite direction. The 
contents of the Z register select the planes that are to be inhibited. The address 
contained in the S register selects the horizontal and vertical stripes to be ener- 
gized. 


VERTICAL 

INHIBIT 

STRIPES 


X-DRIVE 

LINES 

(EVEN) 



(TO SENSE 
AMPLIFIER ) 


Figure 12. Simplified Storage Plane 


STACK 

The 18 storage planes are assembled into a stack as shown on the block diagram 
A thin metal plate between each plane and on the top and bottom of the stack pro- 
vides shielding and acts as a cold plate for cooling. 


HORIZONTAL 
. INHIBIT 
STRIPES 


X>0RIVE 

LINRI 

(ODD) 


HORIZONTAL 
> INHIBIT 
STRIPES 


78.2 
Rev. A 


1700 STORAGE (Cont’d) 


The X and y drive lines thread through the 18 planes as shown in Figure 13, The 
drive lines connect back to the drive deck. Each drive deck connects to 32 drive 
lines on the two sides of the stack as shown on the block diagram. The x and y 
drive decks are identical. The y drive deck mounts on the top of the stack and the 
X drive on the bottom. 



TRANSFORMERS 


Consecutively numbered planes in the top half (nine planes) of the stack are rotated 
900 in respect to each other. For example, plane 1 is rotated 90® counterclockwise 
in respect to plane 0,>etci. The bottom nine planes are also rotated 90^ in respect 
to each other. In this half, plane 16 is rotated 90® in respect to plane 17. The ro- 
tation of planes gives a balance of connections at the corners of the stack. 

One inhibit deck is mounted on each side of the stack and connects to the corners of 
the planes according to the horizontal and vertical stripe connection terminals at 
the corners (caused by the rotation of the planes). For example, vertical inhibit 
stripes 0 and 1 connect at corner B for planes 0, 1, 4, 5, 8, etc. Vertical inhibit 
stripes 2 and 3 connect to corner A for the same planes. Thus, inhibit-deck V21-2 
connects to corners A and B for those planes as shown on the block diagram. The 
two types of inhibit decks (V21 and V20) differ only in the order of the inhibit 
stripes in the planes to which they connect. 


DRIVE DECKS 

One drive deck supplies current to the x drive lines, and the other deck supplies 
current to the y drive lines. The two decks are identical. 

A deck has two printed circuit boards with printed wiring on both surfaces of the 
board. Components are mounted on and between the boards. 

A deck contains a read and write current source £uid circuits to select each of the 
64 drive lines. 


INHIBIT DECK 

The four inhibit decks supply current to the horizontal and vertical inhibit lines. 
The inhibit decks are two types (V21 and V22), and differ only in printed wiring 
layout. 

Inhibit lines on a plane are arranged in four 16 -line groups in horizontal and 
vertical directions. Each deck has six current sources and circuits to select one 
of four groups on nine planes. 


ADDRESS SELECTION 

The address at which a storage reference takes place is determined by the 15 bits 
in the S register. The address is transmitted to the S register from the Y register 
at the beginning of the storage reference. The address in the S register remains 
effective throughout the storage reference. 

Bits 12, 13, and 14 of the address* select the one of eight (maximum storage option) 
banks. If an attempt is made to reference a storage bank that is not plugged in, the 
same address is referenced in another bank that is plugged in. This wrap-around 
storage feature of the 1700 is described in detail in the S register description (page 81). 

The low -order 12 bits of the address select one of 64 x drive lines and one of 64 y 
drive lines during the read and write phases of the storage reference. Bits 0-5 select 
the y drive line, and bits 6-11 select the x drive line. 


Figure 13. X and Y Drive Lines 


78.3 
Rev. A 





1700 STORAGE (Cont'd) 


In the y drive line selection, bits 1,2, and 3 of the address select one of eight 
current source transformers on the y drive deck. Bits 0, 4, and 5 select one of 
eight current diverter circuits. The combination of these two selections selects 
one of 64 drive transformers on the y drive deck which transmits the read and 
write current pulses through the corresponding y drive line. The selection of the 
X drive line functions in an identical manner in the x drive deck with bits 7, 8, and 
9 and bits 6, 10, and 11 respectively. 

Bits 4 and 5 of the address also select one of four inhibit stripes on inhibit decks 
V20-2 and V21-2. Thus, these inhibit decks select one of four vertical inhibit 
stripes on the corresponding planes. Bits 10 and 11 perform an identical function 
in inhibit decks V20-1 and V21-1, selecting one of four horizontal inhibit stripes. 


Z REGISTER 


In storage Write operations, the word in the Z register is replaced by the word 
transferred from the X register. The new word in the Z register is then stored 
at the selected address during the write phase. 


TIMING AND CONTROL 

The timing and control circuit receives input Request Storage and Write signals 
from the external storage and computer accesses. The timing and control circuit, 
in conjunction with the timing chain, then synchronizes and controls the entire 
storage reference operations, such as read, write, and inhibit timing. The timing 
and control circuit also performs such operations as bank selection, priority 
control between the external and computer storage requests, and transmitting the 
Resume signal which releases the computer or external accesses. 


STORAGE BANK CONNECTORS 

Each storage bank connects to the input, output, and control logic through four 
30 -pin connectors. Thus, a storage stack simply plugs into the corresponding 
connectors on the chassis. The connectors are identified, according to the same 
chassis coordinate system as the logic connectors. Inputs and outputs from the 
stack are shown on the logic diagrams in this manner. For example, the output of 
pin 14 on the VI 7 module at C23 (page 42) lists the destination as H08-9. Thus, 
this output connects to connector H8, pin 9. 

The storage module connector format is listed in Table -3,. The table shows the 
format for bank 0. The format for the other banks is the same. 


TABLE 3> 18-BIT STORAGE MODULE CONNECTOR FORMAT 

13^ T3 Ti T/ T3 


PIN 

H8 

H7 

H2 

HI 

PIN 

H8 

H7 

H2 

HI 

1 

Z^ 

*Sense 3 

J3-3 

*Sense 11 

16 

Ground 

J2-14 

slOl 

s® 

2 

*Sense 12 

J2-4 

*Sense 0 

Z2 

17 

Read 


J3-19 


3 

Z5 

*Sense 3 

J3-1 

*Sense 11 

18 

**Adapter +4. 5v 

J2-20 

I 

s® 

4 

={=Sense 12 

J2-2 

*Sense 0 

Z® 

19 

Write 

*Sense 9 

J3-17 

Ground 

5 

7.10 

*Sense 7 

J3-7 

li'Sense 15 

20 

**Adapter +4, 5v 

J2-18 

sio 

s° 

6 

*Sense 16 

J2-8 

*Sense 4 

Z^ 

21 

zi^ 

*Sense 9 

J3-23 

+ 16v Drive 

7 

zi4 

*Sense 7 

J3-5 

*Sense 15 

22 

+6v (Drive) 

+6v Inhibit 
V21B -#1 

sii 

S^ 

8 

*Sense 16 

J2-6 

*Sense 4 

Zl3 

23 

zii 

*Sense 6 

J3-21 

♦Sense 14 

9 


I 

J3-11 


24 

’i'Sense 17 

+8v Inhibit 

*Sense 5 

zi® 

10 

Master Reset 

J2-12 

^Sense 8 

z^^ 

25 

z® 

*Sense 6 


♦Sense 14 

11 

sO 

I 

J3-9 


26 

*Sense 17 

+8v Inhibit 

^Sense 5 


12 

Master Reset 

J2-10 

*Sense 8 


27 

Z^ 

*Sense 2 

Mass Drive 

Adjiistmpnt 

♦Sense 10 

13 

s® 

Ground 

J3-15 

Core Protect 

28 

*Sense 13 

uverioad 

disable 

♦Sense 1 


14 

+6 V In^^ibit V 2 1 B 

J2-16 

Ground 


29 

Z° 

*Sense 2 

Mass JJri^^ 
Adjustment 

♦Sense 10 

15 


Mass Inhibit 
Adjustment 

J3-13 

Core Protect 

30 

*Sense 13 

Overload 

♦Sense 1 

z® 


^Indicates twisted pair 


**Storage module tester input 

78.4 
Rev. H 


The sense line from each plane connects to a corresponding sense amplifier 
circuit. The sense amplifier circuit detects the switching of a core from the "l" 
to the "o’* state. During the read phase of each storage reference, the output of 
the sense amplifiers transfers to the Z register. Thus, in the read phase, the 
Z register contains the word read from the stack. 

In storage Read operations, the word in the Z register is later transferred to the 
X register. The word in the Z register is then restored in the storage stack at 
the selected address during the write phase. 




READ 

WRITE 


Y DRIVE DECK 
(MX) 


I OF e CURRENT TRANSFORMERS 
I OF 6 DIVERTERS 





S REGISTER 


The 15-bit S register contains the address of the current storage reference. The 
bit format of the S register is shown below. 


BANK X DRIVE Y DRIVE 

SELECTION Lt^NE LINE 

' 14 13 12^ II 10 98765432 I 0 



(lOF 8) (I0F4) 


The S register receives inputs from the 1705 external channel through the Address. 
Receiver modules or from the computer Y register. The address is transferred to 
the S register approximately 75 nsec after the initiation of storage. The external 
channel active enable or the computer channel active enable from storage timing 
and control gates the respective input into the S register stages through the inverters 
on the VI 7 modules. 


BANK SELECTION 

Bits 12, 13, and 14 determine the storage bank selection. The Z80 modules perform 
the bank selection. The selection of a given bank by the corresponding Z80 module 
enables the Read and Write (R and W) drive signals to only that storage bank. 

The bank selection circuit performs a wrap-around function in bank selection. For 
example, if the bank-designator bits attempt to select a storage bank not included in 
a particular system, the bank selection circuit selects an existing bank according to 
a fixed order of selection. The table below lists ^ach pqssible storage 
size, the corresponding module and pin connections, and' the storage hank 
for a given bank designation. 

If a particular module size does not exist in a system, pins 5,. 6,. 22 and 1 receive 
+1.2v ("O") inputs. If the banks exist, the pins receive a srd'C'l") input. The input 
pins are grounded on the storage module connectors. For any storage bank option 
less than 20K, Z80 module 2 is removed. 


The high-order three bits select the storage bank; bits 6-11 select the x drive line; 
and bits 0-5 select the y drive line. In addition, bits 4 and 5 select the vertical 
inhibit stripe, and bits 10 and 11 select the horizontal inhibit stripe. 

The S register is contained on four VI 7 modules. The bit positions are arranged 
on the VI 7 modules for the convenience of the format shown above. Thus, each 
module contains two of the low -order drive -line bits, one of the inhibit**stripe bits, 
and one of the bank-selection bits. The high-order bit positions on the VI 7 module 
at D27are not connected since there are only three bank-selection bits. The outputs 
of the low-order three bits on each module and the corresponding fan-out modules 
go to the drive and inhibit decks where the address and inhibit stripe selection is 
made. The output of the bank- selection bits connects to the inputs of bank-selection 
module 1 (*Z80). 


As an example of storage bank selection, assume a bank designator of 6 and a 
storage size of 20K. In this case, pins 5, 6, 22 and 1 in module 1 are grounded 
("l" inputs). In module 2, pin 1 is grounded and pins 5, .6 and 22 receive "0" 
inputs (banks 5, 6, and 7 are not plugged in). Since the bank designator is 6, pins 
14, 13, and 12 on module 1 receive 110 inputs respectively. As a result all bank 
selection outputs of module 1 are disabled. In baric selection, a "l" output of the 
Z80 module disables the selection of the corresponding bank. The ACE AND input 
in module 2 enables the following R and W signals to pass through the output inver- 
ters for pins 27 and 28. These outputs provide Read and Write drive currents for 
bank 4, according to the table below. 


BANK SELECTION TABLE 


STORAGE 

SIZE 

REMOVE 

MODULE 

IN MOD 1 
GND PIN 

IN MOD 2 
GND PIN 

ORDER OF 
BANK ACCESS 
BANK DESIG. 

0 1 2 3 4 5 6 7 

4K 

2 



00000000 

8K 

2 

1 


0 10 10 10 1 

12K 

2 

1, 6 


0 1 2 2 0 1 2 2 

16K 

2 

1.5,6 


01230123 

20K 


1, 5, 6. 22 

22 

01234444 

24K 


1, 5,6.22 

1,22 

0 1 2 3 4 5 4 5 

28K 


1,5,6,22 

1;6,22 

01234566 

32K 


1,5,6,22 

1,5,6,22 

01234567 


80 

Rev.AA 











Z REGISTER 


The Z register serves as an intermediate storage for data being read from storage 
or being written into storage. The 18-bit Z register is contained on nine V47 
modules. The Z register and associated input and control logic is shown on pages 
83 through 99v Except where specifically noted in the text, the following descrip- 
tion of the Z register is based on stages 0 and 1. 


READ OPERATION 

The Z register receives inputs from the sense amplifiers on the read phase at 
approximately 475 nsec of the storage cycle. At this time, the output of inverter B 
gates the output of the sense amplifiers from the selected bank into Z. If a particu- 
lar storage bank option (2-7) is present, the corresponding input to the Z register 
or V84 fan-in module is grounded. For example, if bank 4 is plugged in, pin 14 is 
grounded ("l") causing C to enable the output of the bank 4 sense amplifiers. If a 
bank is not present, the corresponding input pins receive "O" inputs since the sense 
amplifier modules for that bank are not included with the system. 

Sense Amplifiers 

The sense amplifiers for each bank are contained on three V02 modules. Each 
V02 module contains six sense amplifier stages. If a storage bank option is not 
included, the corresponding V02 modules are not plugged into the chassis. 

The detection of a core switching from a "l" to a "O" in a storage plane induces a 
voltage on the sense line. This voltage appears as a "l" to the two inputs of the 
corresponding sense amplifier stage. Assuming the "l" was detected in plane 0 
and bank 0, stage 0 of the V02 module at E06 produces a "l" output at pin 3. At 
475 time of the storage cycle, the Read Strobe gates the "l" output of pin 3 into 
stage 0 of the Z register. 

The Z register diagrams show only the sense amplifier stages for banks 0 and 7. 
The table opposite page 85Tists the locations, test point ,and output pin informa- 
tion for sense amplifier modules for all storage bank options. 


WRITE OPERATION 

In a Write operation, the Z register receives inputs from the 1705 direct storage 
access receivers or the computer X register. If a 1705 option is included in the 
system, the receiver modules are plugged into the chassis. Thus, if an external 
storage write request is accepted by storage control, the Receivers Z signal and 
the write strobe enable the transfer of the receiver outputs to the Z register at 600 
nsec of the storage cycle. If the computer write request is accepted, the X~*-Z trans- 
fer takes place at the same time. Later in the write phase, the "O" bits in the Z regis- 
ter turn on inhibit drive currents for the corresponding planes of the selected bank. 

INHIBIT FAN-OUTS 

Two inhibit fan-out modules connect to each stage of the Z register. The V87 
modules provide inhibit inputs for banks 0 and 1, and the V86 module functions for 


banks 2 through 7. The Inhibit enable which occurs at 675 nsec of the storage cycle 
gates the "O” state of the Z register stages to the inhibit decks on all existing banks. 


PARITY GENERATOR 

The parity generator circuit consists of two VI 8 modules. Each V18 module 
generates parity for nine Z register stages. Both modules operate identically. Thus, 
the following description is based on the V18 module that generates parity for the low- 
order nine stages. 

The VI 8 module generates parity based on three 3- stage groups. The inverter 
inputs to each of the three groups examine the contents of the three stages for an 
odd combination of *'l" bits. For example, if stages 0, 1, and 2 of the Z register 
are all "I's", AND inputs A, C, and E produce a°'l" output of S indicating these 
stages contain an odd number of "l" bits. The output inverters examine the four 
possible odd combinations of the three groups. Thus, if the nine stages contain an 
odd number of bits, the corresponding output is a "O". If the nine stages contain an 
even number of "l" bits, all the outputs are "I's". 


STAGES 16 AND 17 

Stages 16 and 17 (page 99) function differently Tfromr .the other stages. The sense 
amplifier inputs and control for these stages are the same as for the other stages 
However, these stages do not receive inputs from the X register or the external 
receivers during a Write operation. The parity bit (stage 16) receives no inputs 
except from the sense amplifiers. However, the program protect bit (stage 17) is 
set by the following two other conditions: 


1. (Write Protect) (tOO) (Write Strobe) (Z17 = "l") 

2. (Write Protect) (tOO) (Write Strobe) (F8) 

In condition 1, the Write Prot ect function ~ (Ext e rnal Write) (E x ternal Channel. 
Active ) D( External Protect) + (External Protect) (Parity Error) (Storage Protect 
Fault)l + (Compute r Channel Active) (Computer Write) C omputer Protect + 
(Computer Protect) (Parity Error) (Storage Protect Fault)! . 


In condition 2, the Write Protect function = (Parity Error) (Storage Protect, Fault) 
(Write Protect. Bit- = ''l") (Computer Channel Active). The Write Protect Bi t FF is 
set during the computer REG mode in the SPB or CPB instructions with the Interrupt 
condition. 


Thus, in condition 1, the Write Protect function enables the transfer of the previous 
state of Z17 back to stage 17 at 600 nsec of the storage cycle. In condition 2, the 
Writ e Pr otect function enables the setting of stage 17 at 600 nsec on a SPB instruc- 
tion (W). 


82. 

Rev. A 



SENSE AMpL 



notes: 

1. r#| REPRESENTS LINE DRIVER WITH 
— NO OUTPUT DIODE. 

2. SEE OPPOSITE PAGE 87 FOR ZS 
MODULE CABLING. 


PARITY GENERATOR 


A24 

Ivi^ 



CONTROL DATA 
m CORPORATION 

TITt« 

Z REGISTER 

PRODUCT 

1704 

jDIZC |DR«»IR« RO. 

If] 


(STAGES 0 a 1) 

C 60152700 


COMPUTER DIVISION 


I tNCCT 


Mft 


83 



TABLE 4. SENSE AMPLIFIER AND DATA RECEIVER-TRANSMITTER LOCATIONS AND TEST POINTS 


Bit 

DATA 

Receivers Transmitters 

Bank 0 

Bank 1 

Bank 2 

Bank 3 

Bank 4 

Bank 5 

Bank 6 

Bank 7 

Bit 


Out- 

put 

Pin 

Loc. 

T. P. 

Out- 

put 

Pin 

Loc. 

T. P. 

Out- 

put 

Pin 



Out- 

put 

Pin 

Loc. 

1^^ 

Out- 

put 

Pin 

Loc. 





Out- 

put 

Pin 




Loc. 

Input 

Output 

Loc. 

T. P. 

T. P. 

Pin 

T. P. 

Pin 

0 

IE 

)07 

1 

7 

2 

10 

m 


1 

3 

E 

a 

1 

3 

a 

01 

1 

3 

IE 

25 

1 

3 

D 

a 

1 

3 


43 

1 

3 

D 

fl 

1 

3 


57 

1 

3 

0 

1 




17 

3 

12 



2 

4 



2 

4 




4 



2 

4 



2 

4 

fl 

B 


4 




4 

fl 

B 


4 

1 

B 




fl! 

6 




3 




3 

5 



3 

5 



3 

5 



3 

5 

fl 

B 

3 




3 

5 

fl 

fl 

3 



B 

E 

Q 

1 

7 

2 

B 

B 

■ 

4 




4 

2 



4 

2 



4 

2 



4 

2 

fl 

B 

4 

2 



4 

2 



4 


3 


■ 

B 


17 

3 

12 

fl 

■ 


25 



5 

25 







5 

25 



5 

25 



5 




5 

25 

fl 

fl 

5 

25 

4 

B 

B 

fl 

5 

m 

6 

22 

■ 

1 

6 

m 



6 

24 



6 

24 



6 

24 



6 

24 

> 


6 




6 

24 

B 

B 

6 

24 

5 

6 

ID 

09 

1 

m 

B 

10 

fl 


1 




1 

3 

a 

0 

B 

3 

IE 

26 



1 

3 

0 


1 

3 

fl 

9 

1 


fl 

fl 

1 

3 

IE 

58 

1 

3 

6 

7 




4 


B 

12 







2 

4 



EB 

4 



2 

4 



2 

4 

fl 

fl 

2 

4 




4 



2 

4 

7 


■ 

B 

5 





1 


5 



3 

5 

■ 

B 

3 

5 


fl 


5 

fl 


3 

5 



3 

B 

B 

fl 

3 

B 

B 


3 


8 

B 

E 

B 

1 



Q 

fl 

1 





4 

2 



4 

2 

fl 

fl 

4 

2 

fl 


4 

2 



4 

B 

B 


4 

B 

B 


4 

B 

9 

10 

B 

B 

4 


3 

D 

fl 

1 

B 




5 


B 

B 

B 

25 

fl 

fl 

5 

25 

fl 


5 

25 

fl 

fl 


25 

B 

fl 

5 

25 

B 


5 

00 

10 

11 

■ 

fl 

B 

24 

6 

22 

fl 

1 

B 




6 


1 

1 

B 

24 

fl 

fl 

6 


fl 


6 

24 

1 


6 

24 

B 

1 

6 

24 

fl 


6 

24 

11 

12 

B 

fl 


B 


10 

B 

s 

B 




1 

3 

IQ 

B 

1 

3 

IQ 

0 

1 

3 

B 


1 

3 

iQ 

fl 

1 

3 

IE 



56 

1 

3 

fl 


1 

3 

12 

13 

B 

B 

4 

D 

3 

12 

fl 

■ 






4 

■ 

■ 


4 

fl 

■ 


4 

fl 



4 

fl 

1 

2 

4 

B 

fl 


4 

fl 



4 

13 

B 

B 

fl 


m 

6 


fl 

■ 





3 

5 

B 

B 


5 




5 

B 


3 

5 

B 

■ 

3 

5 

B 

fl 

3 

5 

B 



5 

14 

15 

1D12 


D 

2 

10 

fl 

■ 

4 




4 

2 

B 

B 

4 

B 




2 

fl 


4 

2 

B 

■ 

B 

2 

fl 

B 

4 

2 

B 


4 

B 

15 

IB 








5 

25 



5 

25 

B 

B 

5 

|^Q[ 




25 

B 


5 

25 



B 




5 

25 

fl 


5 

101 

16 

a 






> 


6 

24 

fl 

1 

6 

24 

□ 

□ 

6 

24 

■ 

1 


24 

■ 


6 

24 

B 

1 

6 

24 

fl 

■ 

6 

24 

fl 


6 

24 

17 


. 84 

Rev. 4 



















































































































































































TABLE 5. ZS MODULE CABLING 


Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

D07 

3 

J06-A2 

DO 8 

3 

J06-A8 

DO 9 

3 

J06-B4 


5 

J05-A2 


5 

J05-A8 


5 

J05-B4 


6 

J05-A1 


6 

J05-A7 


6 

J05-B3 


8 

J06-A1 


8 

J06-A7 


8 

J06-B3 


13 

J06-A4 


13 

J06-A10 


13 

J06-B6 


14 

J06-A3 


14 

J06-A9 


14 

J06-B5 


15 

J05-A4 


15 

J05-A10 


15 

J05-B6 


16 

J05-A3 


16 

J05-A9 


16 

J05-B5 


21 

J06-A5 


21 

J06-B1 


21 

J06-B7 


23 

J05-A5 


23 

J05-B1 


23 

J05-B7 


25 

J06-A6 


25 

J06-B2 


25 

J06-B8 


27 

J05-A6 


27 

J05-B2 


27 

J05-B8 


Module 

Location 

Pin 

Destination 

Module 

Location 

Pin 

Destination 

DIO 

3 

J06-B10 

Dll 

3 

J06-C6 


5 

J05-B10 


5 

J05-C6 


6 

J05-B9 


6 

J05-C5 


8 

J06-B9 


8 

J06-C5 


13 

J06-C2 


13 

J06-C8 


14 

J06-C1 


14 

J06-C7 


15 

J05-C2 


15 

J05-C8 


16 

J05-C1 


16 

J05-C7 


21 

J06-C3 


21 

J06-C9 


23 

J05-C3 


23 

J05-C9 


25 

J06-C4 


25 

J06-C10 


27 

J05-C4 


27 

J05-C10 





SENSE AMPL 


FROM BANK 
0 SENSE 
{ PLANE 4 ) 


E06 

|V02| 


Z REGISTER 




H02-I 

H02-aO^ 



FROM BANK 
7 SENSE 
(PLANE 4 ) 
H58-6 

H58>e 


FROM BANK 
0 SENSE 
(PLANE 5 ) 

HO 2-2 4 ( 
H02-26 < 


FROM BANK 
7 SENSE" 
(PLANE 5 ) 
H58-24 

H58-26 



E06 

A 

|V02 

)23 \ 

-O^ 

[>21*^ 



E57 

A 

|V02 

^3 1 






notes: 

1, [«] REPRESENTS LINE DRIVER WITH 
— NO OUTPUT DIODE. 

2. SEE OPPOSITE PAGE 87 FOR ZS 
MODULE CABLING. 


PARITY GENERATOR a24 














SENSE AMPL 


FROM BANK 
0 SENSE 
(PLANE 8 ) 
H02-I0 


H02-I2 


FROM BANK 
7 SENSE 
(PLANE 8 ) 
H58-IO 

H58-I2 


FROM BANK 
0 SENSE 
(PLANE 9 ) 
H07-2J 

H07-19 


FROM BANK 
7 SENSE 
(PLANE 9 ) 
H63-ZI 


H63>I9 


E07 



E58 



E07 



E58 



Z REGISTER 



note: 

fo] REPRESENTS LINE DRIVER WITH 
— NO OUTPUT DIODE. 


PARITY GENERATOR a24 




^CONTROL DATA 
m CORPORATION 

TIT« 

Z REGISTER 

rnooucT 

1704 


• IZt 


E9 


COMPUTER DIVISION 

(STAGES 889) 

C 

60152700 

la 



1 r-T*" 91 




SENSE AMPL 


FROM BANK 
0 SENSE 
(PLANE 10 ) 
HOI-27 


HOI-29 


EOT 



FROM BANK 
7 SENSE 
(PLANE 10 ) 

H 57-27 

H57-29 


E58 



FROM BANK 
0 SENSE 


EOT 

^ 1 

|V02 

(PLANE II ) 

H0I-3L 


H01-I ^ 

^21^ 




Z REGISTER 



notes; 

1. [m] represents line driver with 
— NO output diode. 

2. see opposite page 87 FOR ZS 
MODULE CABLING. 


PARITY GENERATOR 






SENSE AMPL 




FROM BANK 
7 SENSE 
(PLANE 13 ) 
H64-30 

H64-28 



Z REGISTER 



notes: 

1. [T| REPRESENTS LINE DRIVER WITH 
— NO OUTPUT DIODE. 

2. SEE OPPOSITE PAGE 87 FOR ZS 
MODULE CABLING. 


PARITY GENERATOR 
f25 


A27 

iviel 



(CONTROL DATA 
CORPORATION 


COMPUTER DIVISION 


Z REGISTER 
(STAGES 12 a 13) 


PRODUCT 

1704 

jllZE 

C 

60152700 



tHCir 

95 





SENSE AMPL 



note; 

[V] REPRESENTS LINE DRIVER WITH 
— NO OUTPUT DIODE. 


PARITY GENERATOR 


A27 

Iviel 



CONTROL DATA 

TITLI 

V CORPORATION 

Z REGISTER 


(STAGES 14 a 15) 

COMPUTER DIVISION 



^mpucT 

1704 

• IZI 

60 V 52700 

■ (V 

a- 


• MCCT 

PA«C 

97 





-LI 

Z REGISTER 
(STAGES 16 a 17) 


ritOOUCT 

1704 






STORAGE INTERFACE 


The storage interface module (V82) provides communication between computer 
control and storage timing and control. The V82 module contains the request 
storage, write, protect and parity fault outputs to internal interrupt, Z -*■ X, 
(Resume) and write protect bit controls. 


REQUEST STORAGE 

The setting of the Request Storage FF by computer control initiates a complete 
storage cycle. The Request Storage FF remains set until the computer Resume 
is issued by storage control at 425 nsec of the storage cycle. A subsequent 
computer request could then be made. However, a storage cycle is not initiated 
Until the Storage Busy condition is disabled at the end of the complete storage cycle. 

The Request Storage FF is set at V050 time of the B cycle if under the following 
conditions: 

(Immediate Operand + RfJI + Read Index) 


conditions. The Write FF is set on the following conditions: 

(Request Storage) [(ADR+REG) [(End Addressing) (STA+STQ4-SPA+RTJ) +INT1 
+(RAD)(ROP)+ Enter] 

Z X 

The Computer Resume signal sets the Z X FF at 450 nsec of a storage reference. 
The actual Z to X register transfer does not take place until 500 nsec. The setting 
of the Write FF blocks the Z to X transfer through inverter F. 


WRITE PROTECT BIT 

The Computer Resume signal sets the Write Protect Bit FF in the REG mode of 
an SPB or CPB instruction if there is no interrupt. The setting of this FF enables 
the setting of the Protect bit(Z17) on the SPB instruction and the clearing of the 
Protectbit on the CPB instruction. 


WRITE 

The Request Storage enable (I) sets the Write FF if a word is to be written in 
storage. Each Request Storage enable clears Write (H) before probing the set 


100 

Rev. A 



A34 



NOTE : 

SEE Z-*»X a REO. STORAGE (P. 39). 




STORAGE TIMING CHAIN 


The storage timing chain circuits control the timing sequence of all storage cycle set and clear which produces the basic storage timing sequence. The timing 

operations. The timing chain is contained on the V69 module with the input and chain goes through three complete sequences for each storage cycle, 

output control circuits on the V89 and V93 modules. 

The storage control circuit initiates the operation of the timing chain with the 
Start Timing Chain signal which sets KOO. Flip-flops KOG through K05 sequentially 



I05-D24 ^ Y S 

103-D23 ^ KOO 

I03-D23 ^ KOI 

103 - 022 ^ K02 

103-022-26 K03 

103-022 ^ K04 

103 -022-6 KOS 

I03-C22-V V 

I03-C22 ^ S 

I03-C22 ^ T 

I03-C22 ^ W 

I03-C22 ^ X 

I03-C22 ^ y 

103 -C22 ^ Z 

103 -0 23- I EARLY X 

103-028 ^ REAO 

105-028 ^ INHIBIT 

105 - 028 ^ WRITE 

99 -B29 ^ SENSE AMPS— Z 

99-B29^ X -*- Z (WRITE ONLY) 

39 -B46-B (REAO ONLY) 



NOTES: 

1. THE UP PORTION OF ALL WAVEFORMS INOICATES THE "l STATE OF THE CORRESPONDING SIGNAL OR ENABLE. 

2. THE STORAGE SEQUENCE SHOWN ASSUMES A COMPUTER REFERENCE THROUGHOUT. THE EXTERNAL 
REFERENCE. SIGNALS ARE IN THE SAME TIME RELATIONSHIP. 


102 

Rev. E 




105 - 013-18 
TO INHIBIT TIMING 


/TO INHIBIT TIMING 








STORAGE TIMING AND CONTROL 


/ 

The storage timing and control circuit controls such functions as Storage Access, 
Storage Protect Fault, Read, Write, Inhibit, Parity Bit, and Parity Fault. The 
timing chain sequences the control functions. The following paragraphs describe 
each of the main functions listed above with reference to the Storage Timing Chain 
(page 102). 


STORAGE ACCESS CONTROL 

Storage access control functions take place on the V90 module. The request storage 
enable from the computer or external interface sets the corresponding Channel 
Active FF. The External Channel Active FF is set at tSO time. The Computer 
Channel Active FF is set at t75 time if the Priority FF (page 103) is not set. The 
setting of either of the Channel Active FFs starts the timing chain and sets the 
Busy FF. The Busy FF blocks the Start Timing Chain output and the setting of the 
Channel Active FFs until Busy is cleared at the end of the present storage reference. 
The setting of the Channel Active FF enables the gating of the corresponding address 
and data (Write only) into the S and Z registers respectively. 


STORAGE PROTECT FAULT CONTROL 

The storage protect fault control is contained on the V94 module. The computer 
and external write and protect inputs enter this module. The state of the protect 
bit (Z17) is gated into inverter G at 525 nsec if the computer or external channels 
are active and the corresponding protect and write inputs are enabled. 

If Z17 equals "l”, the output of G sets the storage protect fault according to the 
following conditions: 

EXTERNAL 

STORAGE PROTECT FAULT = (Z17 = *'l") (525 nsec) (EXTERNAL 
CHANNEL ACTIVE) (EXTERNAL WRITE) (EXTERNAL PROTECT) 

COMPUTER 

STORAGE PROTECT FAULT = (Z17 = "l*') (525 nsec) (COMP UTER 
CHANNEL ACTIVE) (WRITE) [(INSTRUCTION raOTECTED) 

(PROTECT SWITCH ACTIVE)’] 

The above equations show that the storage protect fault is detected if either the 
external or computer accesses attempt to write in a protected address. The setting 
of the Storage Protect Fault FF blocks the X to Z or Receivers to Z transfer and 
transmits the storage protect fault enable to the computer. 


READ, WRITE, AND INHIBIT CONTROL 

The Read, Write, and Inhibit Control FFs enable the corresponding storage phase 
when set. These FFs are contained on the V91 module. These FFs are set at the 
proper times in the storage cycle according to the storage timing sequence 
page 102). 


PARITY BIT AND PARITY FAULT CONTROL 

The parity bit and fault control is contained on the V95 module (page 107). 


Parity Bit Control 

The writing of the parity bit in storage depends on the gate new parity enable from 
the V92 module. A new parity bit is written into storage under the following condi- 
tions; 


GATE NEW PARITY = [EXTE RNAL PROTECT + (PARITY FAULT) 

(STORAGE PROTECT FAULT)] [(EX TERNAL CHANNEL ACTIVE) 
(EXTER NAL WRITE)] + [(PARITY FAULT) (STORAGE PROTECT 
FA ULT) (WRITE PROTECT BIT) (COMPUTER CHA NNEL ACTIVE)] + 
[(PARITY FAULT) (STORAGE PROTECT FAULT + (COMPUTER PRO- 
TECT) (WRITE) (COMPUTER CHANNEL ACTIVE)] 

If any of the conditions in the above equation are satisfied, pin 5 of the V95 module 
receives a "O” input. The outputs of the parity generator modules (VI 8) are sampled. 
If the total number of bits is odd, the Parity Bit FF is not set and the inhibit fan- 
outs receive a "O" input which stores a "O" in bit 16. If the total number of bits is 
even, the inverse operation takes place. 


Parity F ault Detection 

A parity fault is detected at the input inverters to the Parity Fault FF on the V95 
module. The inputs to these inverters compare the parity generator outputs for the 
two halves of the word. If the two halves of the word (including parity bit) both 
contain an odd number of "I's", a parity fault is detected, and the Parity Fault FF 
is set. Likewise, if both halves contain an even number of bits, the Parity Fault FF 
is set. Thus, one-half of the word must contain an even number of "I's" and the 
other half must contain an odd number of "I's" due to the odd parity employed in the 
data word. 

The Parity Fault condition is transmitted to the computer where it is used in the in- 
ternal interrupt and fault indicator circuits. A parity fault also blocks a writ« opera- 
tion if the location is not protected. 


104 

Rev. A 




COMPUTER DIVISION 



When more than one piece of Equipment is connected to the Direct Storage Access (DSA) Bus, 
Cables must be correctly installed to insure proper operatloi of the Scanner. The attached 
Diagram shows three pieces of Equipment using direct storage access, and the correct Cable 
connections for proper Scanner operation in the "First", "Mid", and "Last" settings. If any 
of the Cables are connected other than as shown, the Scanner will not function properly. 

Any change in Scanner priority will require the Equipment to be re-cabled to correspond with 
one of the examples shown. When the Scanner switch is dialed to "Out", that piece of Equipment 
Is effectively removed from the DSA Bus, and the Scanner switches on all other Equlpnent must be 
changed to correspond with their new position on the DSA Bus. 





• NOTE 

"t" indicates terminator 






COMPUTER Je ^ 
CHAN. ACTIVE Q-^ 
I05-C2I-3 T 

EXT. CHAN. ACTIVE ^27 
I05-C2 I- 6 


EXT. WRITE , 
I05-A28-27 


WRITE • i 

PROTECT BITAl^y^ 
I0I-A34-I3 


Lr^EIVE^S^ 2 
[^83-B2l-ll ■’ 

Se5-B22-ll ' 


WRITE 

I05-A28-I3 


EXT. PROTECT A'P 
I05-A28-2I Y 

PARITY FAULTA23 
I07-A25-5 


COMP. PROTECTfU^ 
I05-A28-I7 T 


KOO 

103- D23- 26 


K02 + K03 
105- D28-8 


GATE 

^NEW PARITY 
I I07-A25-28 


f ez- B2I -I5“l 
S85-B22-I5 , 



GRD IF BANK I 
PRESENT 


XOO, X REG 
39-B45-I9 


GRD XF BANK 
2-7 PRESENT 


READ STROBE I 22 

BANK I SENSE 
EI2-4 T 


XOI, X REG 
39- B4 5-26 


t75 

3-C26-26 


WRITE STROBE 
83-B2I -13 



STROBE SENSE AMPL 


STROBE PARITY FAULT 


STROBE WRITE CONTROL - 


ZI6 

99-B29-6 



XOO, X REGISTER 
39-B50-I9 


I I PARITY GENERATOR 


,2 SEE ' Y“ 

■^WGE qA 

83,85, I 

87. 28C> 


39-B50-20 I I L 89.SI 
J I 


XMTR 

83-D07- 17 


LBANK 2,7 INHIBIT 


k WRITE DATA ABORTED 
r 33-D39-8 


I PARITY BIT I 
>39-840-15 



(K04) (X)t75 J ,0 

I05-D28-I9 


t50 

3- C26-6 


CLEAR PARITY ERROR 

23-C40-9 Ya 


SEE ' N 

PAGE a C 


GATE NEW 
I 1 PARITY 


EXT CHAN ACTIVE 
I05-C2I -14 


L WRITE CONTROL I05-C2I-I2 
/PARITY FAULT 
I07-A26-23 


READ 

81 - C27-27 


EXT CHAN ACTIVE 
I05-C2I-I0 ( 


too 

3 - B4I -6 ' 


600 l05-C2l-28f 



.CONTROL DATA 
CORPORATION 


COMPUTER DIVISION 


STORAGE TIMING AND 
CONTROL 


C 60152700 



X AND Y DRIVE DECKS (TYPE Z77) 


The two type MX drive decks control the selection of the x and y drive lines. The 
y drive deck mounts on the top of the stack and the x drive deck on the bottom. The 
two decks are physically and logically identical. 

The low -order 6 bits of the address select the y drive line, and the high-order 
6 bits select the x drive line, thus selecting one of 4096 cores in each plane. The 
following description applies specifically to the y drive deck. However, the descrip- 
tion also applies to the x drive deck with the interchange of bit positions. 

The drive circuits have separate primary read (RC) and write (WC) current sources, 
and both feed eight current transformers through a double primary winding circuit. 
These transformers provide eight current sources. Each source feeds one drive 
line transformer in each of eight groups. The drive transformer secondary winding 
connects to the ends of the drive line which threads all 18 planes. 

Each of eight diverter circuits feeds eight successive driver transformers. The 
selection of one of eight diverters diverts current to the proper drive line trans- 
former and its drive line. Thus, a single current source is diverted to one of the 
64 drive lines. Translations of S register bits 1, 2, and 3 select one of eight 
current source transformers. S register bits 0, 4, and 5 select one of eight 
diverters. 

Since both drive decks are turned on at the same time, a coincident current passes 
through one core in each plane. 

The 64 drive transformers on each deck are so arranged that the 32 odd line trans- 
formers are on one edge and the 32 even are on the opposite edge (page 79). Thus, 
opposite sides of the deck drive successive lines. This arrangement provides an 
opposing current relationship with the inhibit drive lines. 


CURRENT SOURCE 

The primary read or write current source consists of a large inductance connected 
between the +6v supply and the eight current transformers. Transistor Q1 (and Q2) 
and its collector resistor (several in parallel) shunt current of about 250 ma to 
ground during non-write-or-read times. The load network keeps the power supply 
load nearly constant at all times. After losses in the current transformer and 
drive line transformer, approximately 200 ma pass through the drive line during 
the storage cycle. 


Bits 1, 2, and 3 of the address select one of eight transformers from a 2 -by -4 
transformer matrix. Bits 2 and 3 select one of four transformer groups, and bit 1 
selects one of two in that group. The Read or Write Drive signal is combined with 
the one of two selection. The simplified drive and diverter circuits shown in the 
lower left-hand corner of the diagram assumes a --100- binary code in the 3 -bit 
drive position. The example also shows that transistors Q5 and Q6 turn off (shown 
as an AND) and Q7 turns on to select transformers T4 and T5 in the one of four 
group; transistors Q8 and Q9 turn off and Q3 turns on to Select the read side of T4. 

Read load network transistor Q1 turns off, and current flows from ground to the 

+6v source through transistors Q7 and Q3, transformer T4, diode CRl, and inductor LI. 

A high impedance is presented to inductor LI when readHoad network transistor Q1 
turns off, and the voltage level at the junction of diode CRl and inductor LI rises 
rapidly. However, diode CR4 conducts to place stabistor CRIO in the circuit, and 
the latter limits the peak voltage at the junction to 15v. Current loss in T4 is about 
25, ma, so 225 ma flow in the secondary and is diverted to a drive: transformer. 

The circuit operates in a similar manner in the write cycle except that the polarities 
in the current transformer are reversed. 


DIVERTER CIRCUITS 

The eight diverter circuits divert read and write current to the drive transformers. 

Each circuit feeds eight drive transformers, one for each current source transformer. 
Thus, the selected current source transformer drives eight lines and only one of the 
eight is diverted. 

The diagram shows one of eight diverter circuits and its selection from the 3 address 
bits used for divert. The collectors of QIO, Qll, and Q12 feed the base of NPN 
transistor Q14 directly and the base of PNP transistor Q15 indirectly -via transisto'r Q13 
which inverts the combined collector signal. The action establishes positive and nega- 
tive turn-on signals for the bases of Q14 and Q15. Emitter bias on these two transistors 
is established by the divider network of ROl, COl, and diodes CR7, 8, and 9. The 
diode threshold is about 0. 7v for a combined drop of about 2. 2v and proper emitter bias. 

The circuit operates in a similar manner in the write cycle except the polarities in the 
current transformers are reversed. 


108 

Rev. H 








INHIBIT DRIVE DECKS (TYPES V20 AND V21) 


Four inhibit decks provide the inhibit current for the writing of a "0" in the 
corresponding plane. An inhibit deck is mounted on each of the four sides of the 
stack (page 79). 

The inhibit lines in each plane are divided into four vertical and four horizontal 
stripes or quadrants. Each quadrant threads through 16 rows (horizontal) or 
columns (vertical) of cores. If a particular stage of the Z register contains a "O" 
at the time of the inhibit phase of the storage cycle, one horizontal and one vertical 
inhibit quadrant is energized in the corresponding plane simultaneously with the 


write current. Thus, one 16-by-16 core portion of the plane receives full inhibit 
current. The quadrant that receives full inhibit current corresponds to the portion 
of the plane containing the selected core, S register bits 4 and 5 select the vertical 
inhibit quadrant and bits 10 and 11 select the horizontal quadrant. 

Two types of inhibit decks are used, the V20 and V21. The two types differ only in 
the order of inhibit quadrant connections. There are two of each type mounted on 
the stack. The tables on the diagram list the inhibit decks and the Z register and 
S register connections. 


110 

Rev. A 



© QUADRANT 

SELE^N ©©©©©©©©© 


CURRENT SOURCE 


VERTICAL INHIBIT 
DECK (V20-2) 


INHIBIT TRANSFORMER 


© QUADRANT \ ^ ^ 

se lectio n 01 10 



© © © © © 


0 CURRENT SOURCE 


INHIBIT TRANSFORMER 


VERTICAL INHIBIT 
DECK (V2I-2) V, 


0 CODES ZO~Z0 HAVE THE FOLLOWING SIGNIFICANCE 


MODULE 28 z 6 Z® Z< z3 z2 z' zO 


V20-I 16 IS 12 


V20-2 17 16 13 12 9 7 


V2I-I 17 14 13 10 9 6 5 2 I 


V2I- 2 15 14 II 10 


INHIBIT I 
* VOLTAGE , 

I REGULATOR ' 

1 . J 


© r- 


REGULATED 
SOURCE VOLTAGE 


I HORIZONTAL 
' INHIBIT 
I DECK 
I (V20-I) 


0 CODES S^,S5 have THE 
FOLLOWING significance 


MODULE 

S5 

s-» 

V20- 1 

s'> 

sio 

V20- 2 

S5 

s^ 

V2I- 1 

s" 

sio 

V2I - 2 

S5 

s4 


0 :::::: 


HORIZONTAL 

INHIBIT 

DECK 

(V2I-I) 


EQUIVALENT 
S REGISTER BIT 


CONTROL DATA 

Tint 

raoMCT 

1704 


INHIBIT DRIVE DECKS 

C 60152700 

COMPUTER DIVISION 






TRANSFERS 



ADDRESSING MODES 


The table below shows the register transfers necessary in forming 
the 32 possible effective address modes. The storage reference instruc- 
tions contain three fields: Instruction, Address Mode, and Delta. The 
format of the storage reference instruction is shown in the lower right hand 
corner. The effective address is formed by setting various combinations 
of the four address mode bits and delta. Delta is a signed 8-bit address 
modifier where the most significant bit (bit 7) is the sign bit. 


The computer assembles the effective address in the following 
order if the corresponding address flag is set, 

1) checks r and A and forms Pt-A , P+1 or A , 

2) checks ind and completes indirect addressing, 

3) checks q and adds the contents of the Q register, 

4) checks i and adds the contents of storage location OOFF, 


112.1 

Rev. A 



Pll 

X 0 -X 7 
Fio 
. Fg 

Fb 

Fe-F„ 

HEXADECIMAL 

r 

F|| 

X 0 -X 7 

F|o 

Fg 

Fe 

Fe-Fn 

HEXADECIMAL 

EFFECTIVE 

“ADDRESS 

A»0 


IND 

IND 

IND 

IND 

q 

q 

q 

ICT 

q 

q 

q 

q 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

i 

F 

E 

D 

c 

B 

A 

9 

8 

F 

E 

D 

c 

B 

A 

9 

6 

EFFECTIVE. 

ADDRESS" 

P*-1*Y 

P'l^P 

P - l*Y 
P- l*P 

PH*Y 

P+I^P 

P H *Y 
PH»P 

Pi-I*Y 

PH-*P 

p+i-*^ 

p+i*p 

P+I*Y 

P^I*P 

P+|-*Y 

P+I»P 

X+Y*Y 

X+Y*Y 

xy-Y-^Y 

X+Y<»Y 

X+Y*Y 

Y'Q*Y 

X+Y*Y 
Y -Q*Y 

X+Y*Y 

X+Y*Y 

Y*S 

Y-^ 

Y-^ 

Y*5 

Y*5 

Yt6 

Y*S 

Y*S 

Z-*X 
XH Y-«^ 

Z*X 

XtY*Y 

Z*X 

X+Y^Y 

Z*X 

X+Y-iH" 

Z-i^ 

X+Y-^ 

Z-*^ 

Xl-Y-^ 

Y+0*Y 

2*X 

X+Y*Y 

XfY-*Y 

Yi« 

Y*S 

Y*5 

Y»S 

Y*5 

Y-S 

Y*S 

Y-*S 

!-► Z*X 
X*Y 
BIT II 

i 

YES 

Y*S 




r-». Z*X 
X*Y 
BIT 

i 

YES 
Y»S 







Y-Q*r 

Y -Q-vir 



Y-Q*Y 

Y^O*Y 



OUFF*S 

OOFF*S 

00FF-.6 

OOFF«.S 

OOFF*S 

OOFF*S 

OOFF*S 

OOFF^S 

Z-»X 

X-Y-»Y 

Z*X 

X^Y-^ 

Z-^ 

X»YVf 

Z-X 
X • Y*Y 

X-Y*Y 

- 


^ ■ r^y 

Y»S 

Y*S 

Y*S 

Y-^ 

Y-S 

Y*S 

Y*6 

Y*S 

Y*5 

y^S 



Y*S 

r*S 

y-*s 


: P- 1 • 

PI • 

Q: ■ DOFF) 

i p* 1 ‘• 
p. 1 , !- 

■ QI 

LP*-! *• 

■>PH)> 

;OOFF) 

1 P^l ► 
■PH); 

P^-lf 

(P^l) + 
iQl't-OOFF) 

P. 1 ^ 

P. H • 
■QJ 

PH r 
■PH / • 
■ OOFF 1 

P- 1 • 
P' 1 ; 

(P--A • 
^QJ ■ 
OOFF 

P-a ■ 
Q 

p- a ■ 
OOFF 

;»• a 

u ■ 

GCf F 

p-a 

u 

Pa 

fJOFF 

p a 


NOTES; 

1. r = RELATIVE ADDRESSING 

: . ind Fj^ - indirect addressing 
L. q F - USE Q REGISTER AS INDEX 

i F - USE ADDRESS DOFF AS INDEX 

PARENTHESES USED IN THE EFFECTIVE ADDRESS INDICATE CONTENTS OF". 


15 12 

W 

10 

9 

8 

7 0 

INSTRUCTION 

0 

H 

0 

0 

DELTA (A) 


J 


ADDRESS 

MODE 


STORAGE REFERENCE FORMAT 


i|^ CONTROL DATA 

TITLt 

m CORPORATION 

ADDRESSING MODES FOR 

DEVELOPMENT 

STORAGE REFERENCE 

DIVISION 

INSTRUCTIONS (D 


PKOOUCT 

1704 

•tzt 

C 

60152700 

RIV 


I tHCCT I PA«t 




A«0 


HEXADECIMAL 


EFFECTIVE. 

ADDRESS 


z*x 

X- 


IND 


IND 


p - iw 
p- i*p 


P+|*Y 

P-I*P 


P-t-|*Y 

P+I*P 


P-I»Y 

P+|*P 


P+I»Y 

P+|*P 


► Z*X 

X*Y 

BIT 15 

i 

YES 
- Y*S 



P- I 1 - 
• OOFF ; 


2*X 

Xvi- 


Y-Q*Y 

Y-Q*X 


,Q;. 

I OOFF ; 




P+1*Y 

P+I*P 


2*X 

X-*^ 


X*Y*Y 

X-Yt^ 


P+IVY 

P-H*P 


L. r F^^- RELATIVE ADDRESSING 
ind F| - INDIRECT ADDRESSING 
q F - USE U REGISTER AS INDEX 
i F. - USE ADDRESS OOFF I- " ,. .! AS INDEX 
: . PARENTHESES USED IN THE EFFECTIVE ADDRESS INDICATE -CONTENTS OF”. 

(D EFFECTIVE ADDRESS OPERAND FOR READ OPERAND INSTURCTIONS. 


HEXADECIMAL 



o*^u 

0-X^ 

o*Xu 

o*«u 

O-Xy 

0*Xy 

o*Xu 

O^y 


X*Y 

X*Y 

X*Y 

X*Y 

X*Y 

X»Y 

X*Y 

A*y 


Y*S 

Y*S 

Y*S 

Y*S 







r*- 

X*Y 

BIT 15 I 

i 

YES 
— Y*5 

/ 

- 






Y-^a*Y 

Y*0*Y 



Yt0-*V 

Y-Q*Y 




OOFF*S 


00FF«6 


OOFF*S 


OOFF*S 



z*x 


z*x 


z»x 


.•A 



X-Y*Y 


A • Y*Y 


X- V^Y 


XY-Y 



Y*S 

Y*5 

Y*S 

Y*S 

Y*S 

Y*S 

Y«6 

Y*S 


!AJ* Q)- 

OOFF ) 

' Ai • Q' 

A ,. • 

OOFF) 

A) 

A - Q, * 
OOFF ; 

A • Q, 

L • DOFF. 

A 


EFFECTIVE 

ADDRESS 


15 12 

II 

10 

9 

8 

7 0 

INSTRUCTION 

0 

H 

0 

0 

DELTA (5) 


ADDRESS 

MODE 


STORAGE REFERENCE FORMAT 


f- 


CONTROL DATA 
CORPORATION 


TITLI 

ADDRESSING MODES FOR 


pROBuer 

1704 

• IZI IBRAWII 


DEVELOPMENT STORAGE REFERENCE 

DIVISION INSTRUCTIONS (?) 


C I 60152700 

■ ■NCEtIr**! 






STO TRANSFERS 


The following table shows the transfers and commands necessary The sequence paths for entering and exiting STO mode are shown 

for instructions using the Store Operand mode (STO). Storage is requested below, 

at time B050 for every STO instruction. 


ROP 



U6 

Rev. A 




STORE OPERAND MODE (STO) 


















REG TRANSFERS 


The following table shows the transfers and commands necessary 
for instructions using the Register Transfer mode (REG). The table is 
especially useful for showing the absence of certain conditions and trans- 
fers during the execution of the listed instructions. For example, at time 
BlOO the Adder — ► Y, P transfer is not used for the EXI, SPB and CPB 
instructions. Also, note that a C cycle occurs during a Shift instruction 
when the shift count i 0. 


The sequence paths for entering and exiting the REG mode 
shown below: 


tXX SPB -t- CPB 



I 

RNZ 


are 


118 

Rev. A 




REGISTER 


■00-h 


100 -h 


A 200-^ 


2504- 


50- 


B 200- 


300- 

325 


SLS 


3004- t I ,P*ADDER 4- 


-oo4- 


REQ. STORAGE 
SET STOP 1 


1004- ADDER*Y,P 


■ CLEAR REG. 
•SET STOP 2 


ENQ 


ENA 


INA 


INQ 


X-*ADDENO 


. A^ADDER 
X^ODEND 


Q«ADOER 

X*AUGEND 


ADDERM3 

,P*ADDER 


ADDER*A 
■ • I ,P*ADDER 


ADDER*A 
" -^1 ,P*ADOER 


ADDER*Q 
■ -I ,P*ADDER 


-LrEQ. STORAGE _L REQ. STORAGE 4- STORAGE i- STORAGE 


- ADOER*Y,P -A- 


- CLEAR REG. -4- CLEAR REG. J- CLEAR REG. 


00 


MODE (REG) 



SHI 

FTS 

INP + OUT 

EXI 

SKIPS 

SPB+CPB 

EIN+IIN 

SHIFT COUNT 
= 0 

SHIFT COUNT 
?feO 

X+AUGEND 


X-^UGEND 





P+ADDER 

XMODEND 

(LOWER 4) 

■ Q*ADDER 


" X*ADDEND 

~ X*ADDENO “ 



P*A0DER 







_ SET + CLEAR 







SKIP FF 









_ CLR ENABLE 







INT UIN) 



- STOP AND 






- SET SHIFT CYCLE 

WAIT FOR reply 







AODER-P 1 REJECT) 

ADDER*Y 

AODER*P (SKIP) 

ADOER*V 


ADDER*Y 

aoder^y 

+1 ,P*ADDER 

1 1 ,P*AODER 

‘1 ,P-*-ADDER 

" i- 1 , P^ADDER 


<l,P*ADOER 

“ A OR Q •ADDER" 

I '0>A 






SET L.P. 







- SET SHIFT R +L 





- 

. SET EARLY B - 

- SET DECR.Y 





- 

- 

- SET EARLY C 







DECR Y 

— 

- 

- 

- 

- 

- SET B CYCLE - 

“ SET C CYCLE “ 







C CYCLE 

_ REQ. STORAGE _ 

_ REQ. STORAGE _ 

. REQ. STORAGE _ 

_ REQ. STORAGE _ 

_ REQ. STORAGE _ 

_ REQ. STORAGE _ 

REQ. STORAGE _ 

- ADDER*Y,P 

- 

_ ADD£R*Y,P _ 

- 

.AODER*Y,P 

_ adder-y.p 

_ ADDER-Y.P 

SET RNI 

SET ROP 

SET RNI 

SET ROP 

SET RNI 

SET RNI 

SET RNI 




CLEAR RNI 




- 

SET ENABLE I NT 


- 

_ SET ENABLE INT 



- CLEAR REG. 

- CLEAR REG. - 

_ CLEAR REG. - 

- CLEAR REG. 

_ CLEAR REG. 

_ CLEAR REG. 

- CLEAR REG. _ 

- 

- 

- 

- 

- 

- 

- 


00 


100 


200 


•300 


00 


100 


■200 


•300 


■00 




CONTROL DATA 
CORPORATION 


TITL* 

REG TRANSFERS 


DEVELOPMENT 

DIVISION 


I raOMCT 

1704 


60152700 

~T 




119 



ROP TRANSFERS 


The following table shows the transfers and commands necessary 
for instructions using the Read Operand mode (ROP). At time AOOO the 
computer receives a Storage Resume signal and at time B050 storage is 
requested. Note that a C cycle occurs during the ROP mode for MUI and 
DVI instructions. 


The sequence paths for entering and exiting the ROP mode are 
shown below: 


EXI + SPB + CPB 



RAO 


120 

Rev. A 




READ OPERAND MODE (ROP) 


AND EOR 


AODER*X 
- +) ,P*A0DER 


adder*p,y adoer*p,y 

OAODER X^ADDEND 

X>AUG£ND A*ADDER SET LP 


ADDER*P.Y ADOER*P,Y 

■ X^ADDENO - 4 - A*ADDER 
A^ADDER SET XR X-*ADDEND 





















THIS TABLE SHOWS THE TRANSFERS THAT MAY OCCUR DURING THE LAST TIME 
OF THE ADDRESSING SEQUENCE AND THE TRANSITION TO THE NEXT SEQUENCE 
(B CYCLE OF ADDRESSING) 


.REQUEST STORAGE 
'BLOCK REG.) 


(MUl) (A NEG) -r{DVl) (Q NEG) 


SET ROP 
(END ADOR) 


SET STO 
(END ADDR) 


SET STO 
(END ADDR) 


SET STO 
(END ADDR) 


ADDER*A 
CLEAR ADOR. 


ADDER*/ 
CLEAR ADDR. 


ADDER*X 
CLEAR ADOR. 


ADDER*X 
CLEAR ADDR. 


AODER-*X 
CLEAR ADDR. 


, CONTROL DATA 
CORPORATION 


B CYCLE TRANSFERS 


DEVELOPMENT 

DIVISION 













C CYCLE TRANSFERS 


The following table shows the transfers and commands necessary 
during the C cycle of Shift, MUI,and DVI instructions. Time 150 occurs 
100 nsec early for Shift and MUI instructions when the short cycle through 
the Adder/Shifter is used. This effectively reduces the Adder/Shifter 


time from 200 nsec to 100 nsec. A DVI instruction uses the complete 
Adder/ Shifter and therefore does not use the short cycle. 

If YOO-04 ^ 0 at the end of the C cycle, the C cycle is repeated. If 
YOO-04 = 0 at the end of the C cycle, the B cycle is initiated. 


124 

Rev. A 



THAI 
( HERAT 






POWER 

DISTRIBUTION 

BOX 

ASSEMBLY A4 


MONITOR PANEL ASSEMBLY Al 




BLOWER ASSEMBLY 
A3 


+ 6V POWER MODULE 

Pri I 


-6V POWER MODULE 



TB3|il TBl| A3 ^4 ^5 ^6 | 

NEUTRAL 01 02 03 -6V COM +6V V ^ 1 

jTiN ' ^ ^ ' TO CBI 

^ . TO METER 


NOTE : 

^ CONNECTORS Jl TO J7 CAN HAVE ANY NUMBER 
^ (UP TO SEVEN) OF +6V OR -6V POWER 
MODULES connected TO THEM. 


POWER CONTROL PANEL 
ASSEMBLY A2 


1 Z 3 4 S 6 

JZ 

1 2 3 4 5 « 

-6V POWER 
MODULE 

WL-J8I33600 


+6V POWER 
MODULE 

WL-I8ISS700 


CONTROL DATA 

T«TLt 

^ CORPORATION 

POWER DISTRIBUTION 

COMPUTER DIVISION 

VERTICAL AUXILIARY CABINET 




POWER AND CABLING 


The following diagrams may be found in the 1700 Site Preparation manual. Pub. 
No. 60158400. 

Power Distribution, 50 Cycle Internal M-G. 

Power Distribution, 60 Cycle Internal M-G. 

Typical 1700 System Using Both Internal and External M-G Sets, 

Typical 1700 System Using an External M-G Set. 


























CONTROL PANEL 


HIGH TEMP 

TEMP WARN. 

TOP ALARM 

CABINET 24 VAC 


ABCDHFEJKLMNPR 


OUTPUT 
FROM 50 ~ 

transformer 


© © 


o o 6 6 o 9 

W5 W6 f 

o ,o .o ,o ,o .o 


JUMPER FOR 
EXTERNAL 
CONTROL 



if. I 

P ASSEMBLY 

lT- -I 


TO FRAME GRD CONNECTOR PANEL 



r IN cabinet”! 

' fi r 

i_r_ u 


to logic J drive 
CHASSIS \ protect 


DRIVE r ^ 

PROTECT 4^ 

r *< 

MASTER I 
CLEAR 6 

L ‘ 



0 JUMPER IF PINS I a 2 OF TBS 
IF TOP CABNET NOT USED 


0 WIRE EXISTS ONLY WITH 50~ 


0 CONTACTS OF Kl HAVE 0.1 SEC 

delay on de-energization. 

0 FRAME AND LOGIC GROUNDS ARE 

normally connected together 

WITHIN THE CABINET. 

0 ALL MACHINES SHALL BE WIRED 

FOR 6O~,3 0 INTERNAL CONTROL. 


0 CONNECTIONS FOR 1700 POWER DISTRIBUTION ARE AS FOLLOWS . 
208/120 V, 60"-, 3 0 CONTROL 1| 398/230V, 50 3 0 COr 


398/230V, 5O"*,30 CONTROL 

INTERNAL 

EXTERNAL 

CONTROL 

CONTROL 

W4 Wl 

W4 —*■ Wl 

W5 —*■ Wl 

W5 — ► Wl 

W6 — ► Wl 

W2 — *■ W3 


CONTROL DATA 

4^ CORPORATION 1700 POWER DISTRIBUTION 

BOX, SCHEMATIC. 

COMPUTER DIVISION ASSEMBLY- A7 

























MASS , 

DRIVE I 

ADJUST . t 



OO OOOOOOOO 
BUSBAR LOSIC -6V 


ooooA ooooool 


000000066 
BUSBAR LOGIC +6V 


TBS TBI 


A 

CONTROL DATA 
CORPORATION 

TITLl 

LOGIC AND MEMORY 

PRODUCT 

1700 

2 1 2 
1 

-k 



POWER SUPPLIES 
CENTRAL COMPUTER CABINET 

C 60152700 

J N 

-* IIOV AC GO~ 1 

n .. 

j 2 

COMPUTER DIVISION 

1 B«^^ WwfTii w 1 &r« wMOfiPW 1 

iMfIT 

137 








note: contacts of relay KI have I.O second delay when relay is OE'ENERSIZEO. 



















5 AMP 


DELTA -STAR TRANSFORMER 


INPUT POWER 


400~ 
208 V 


{ 



* note : replace O.S amp circuit breaker CBI with 1 AMP 

CIRCUIT BREAKER UPON FAILURE. SEE ECO 16529, 


20 AMP 


T2 


DELTA- STAR TRANSFORMER 


400- J 02 
208V n 



TPI 

-<5) 


7 

■ 1 








8 


>4 

9 



10 


If 





Cl 

4000 ^iF 
50VDC 





CONTROL OATA 


DEVELOPMENT 

DIVISION 


400 

TERMINATOR 

POWER SUPPLY 40 VDC 














COMPUTER DIVISION 










— V ' 

OROUNO 

TERM 

TEMP 

EXT 400 >** 400 ~ PWR 

INPUT TO OPTIONS 

50/80 - 
INPUT 



POWER 

A7 

DISTRIBUTION BOX 


}I4900 

WIRES GOING TO OR COMING FROM 
EMBLY A7 ARE FOR REFERENCE ONLY 
ARE CALLED OUT ON WL- 18147000. 

® TRANSFORMER AND WIRE EXIST 
ONLY IN 90 CYCLE MACHINE. 



A8 

M-G BOX 


tB2 



CBI 

J 

6 
X 1 

1 2 


50 ~ 

TRANSFORMER 


CONTROL DATA 
m CORPORATION 

TITLt 

WIRING DIAGRAM, CABINET 

COMPUTER DIVISION 

POWER DISTRIBUTION 


TB. 


A9 

CONNECTOR 

PANEL 


700-B 


60152700 























LOGIC POWER SUPPLY 
























CONTROL PANEL 


ON WARN. TEMP 


8COH FEJKLMNPRju3 


HIGH TEMP 

TEMP WARN. 

TOP ALARM 

CABINET 24 VAC 




M-G ASSEMBLY 


OOTPUT 
FROM 50- 
TRANSFORMER 


® © 


O O 6 6 O 6 

WS W6 

.9 .o o ,o o 


JUMPER FOR 
EXTERNAL 
CONTROL 


rj- -1 

l"'U I 

\ assembly 

L.T- J 


r IN CABINET 

BLOWER 

COMPARTMENT! 

I 

1*'^ 


TO FRAME GRO ’’’O CONNECTOR PANEL 




TO LOGIC I DRIVE 
CHASSIS 1 PROTEC 


DRIVE J 
PROTECT H 

MASTER J 
CLEAR 


0 JUMPER PINS I B 2 OF TBS 
IF TOP CABINET NOT USED 


0 WIRE EXISTS ONLY WITH SO ~ 


0 CONTACTS OF XI HAVE 0.5 SEC 
delay ON DE-ENERGIZATION. 

0 FRAME AND LOGIC GROUNDS ARE 
NORMALLY CONNECTED TOGETHER 
WITHIN THE CABINET. 

0 ALL MACHINES SHALL BE WIRED 

FOR 6O~,3 0 INTERNAL CONTROL. 


0 CONTACTS OF K5 HAVE 5 SEC DELAY ON ENERGIZATION. 

0 CONNECTIONS TOR 1700 POWER DISTRIBUTION ARE AS FOLLOWS. 


208/I20V, G0~, 30 CONTROL 

398/230V, SO 30 CONTROL 

internal 

CONTROL 

EXTERNAL 

CONTROL 

INTERNAL 

CONTROL 

external 

CONTROL 

W7 — W4 
W8 — ► W5 
W9 — ► W6 

W7 — *- W4 
WB —*■ W5 
*2 —*■ W3 

W4 Wl 

W5 — ► Wl 
W€ — *- Wl 

W4 — ► Wl 
W5 — »• Wl 
W2 — »• W3 


j TO MEMORY 
> AND Logic 

I SUPPLY BLOWERS 



C62> GND j 

I9-C62-2S 




Jffi, CONTROL DATA 


'5flT CORPORATION 

1700 POWER DISTRIBUTION 


BOX, SCHEMATIC. 

COMPUTER DIVISION 

ASSEMBLY - A7 





< 


o 


UJ 


RAW CLOCK FANOUT 
t50 a t75 


Z FAN-IN, BITS 6-8 


Z FAN-IN, BITS I5H7 


Z REGISTER 

4 BITS 16,17 


2 Z FAN-IN, BITS 0-2 

d_ BANK DRIVE SELECTION 
• BANKS 4-7 

BANK DRIVE SELECTION 
“ BANKS 0-3 

RAW CLOCK FANOUT 
" tSO a t75 


READ/WRITE INHIBIT FF 

S REGISTER 

BITS 8,9,11 

S REGISTER 

BITS 6,7,10,14 

logic function- MISC. 


BANK 3 SENSE AMPS L. 
t 8ITSI2-I7r^ 


TRANSMITTER; 

READ, WRITE , W 5 0, 
PROGRAM PROTECT 

transmitter; mc aq, 

MC EXT., ZI7 

TRANSMITTER/RECEIVER 
STORAGE DATA BIT 15 


BANK I SENSE AMPS I, 
BITS o-5r 


Z FANOUT BANK 0.1 I. 
♦ BITS12-I7r 


TRANSMITTER/RECEIVER \ 
STORAGE DATA BITS 0-2| ; 


ADDRESS RECEIVERS | 
♦ bits 8,9,10,11,14 ; 


2 FANOUT BANK 0,1 < 

BITS 0-5 ‘ 

BANK 0 sense AMPS c 
♦ BITS 12-17 ‘ 


BANK 0 SENSE AMPS 


ADDRESS RECEIVERS I 
BITS 0,1,2,4,12 I 


CONTROL RECEIVERS 


CONTROL transmitters! 







o 


UJ 


REGISTER DISPLAY, 
BITS 8-15 


REGISTER DISPLAY, 


t PANEL SWITCH CONTROLS I io "- _ 


RAW CLOCK FANOUT, 

too 


SHIFT SIGNAL FAN-OUTS I 


n XR a LP CONTROLS 


LOGIC VOLTAGE 
SENSOR 


RAW CLOCK FAN-OUT, 


« SHIFT CYCLE FF 


AUGEND INPUT CONTROLS l 


AUGEND INPUT CONTROLS I 


AUGEND INPUT 
TRANSFERS (Y,X) 


STO 1 FAN-OUT a 
ADDEND INPUT CONTROL! 


ADDEND INPUT 
TRANSFERS (Q,X) 


ADDEND INPUT CONTROLS 


ADDEND INPUT 
TRANSFERS {P, MASK) 


F TRANSLATIONS 


SECTION I, LOOK AHEAD 


SECTION 0, LOOK AHEAD I 


ADDRESS CONTROL H 


ADDER, GROUP 5 


ADDER. GROUP 7 


ADDER, GROUP 2 


ADDER, GROUP 


ADDER/SHIFTER FAN-OUT, I 
BITS 3.4,9,10 I 


ADDER/SHIFTER FAN-OUT, I 
BITS 1,2,11,12 I 


ADDER/SHIFTER FAN-OUX j 
BITS 0,13-15 : 


AUGEND, BITS 3,4.9,10 


AUGEND, BITS 1,2,11,12 


AUGEND, BITS 0,13-15 


ADDEND, BITS 3.4.9.10 


ADDEND. BITS 1,2,11,12 


ADDEND, BITS 0,13-15 


F TRANSLATIONS 


F TRANSLATIONS 


Y REGISTER, ^ 

BITS 0-6, 8 > 

Y REGISTER, - 

BITS 7,9-15 > 

Y REGISTER FAN-OUT, - 


X REGISTER FAN-IN, 
BITS 0-7 
X REGISTER FANHN, 
BITS 8-15 


X REGISTER, 

BITS 0-7 


A REGISTER FAN-IN, 


ROP 1 FAN-OUT a 
A REGISTER FAN-IN, 
BITS 6-9 

A REGISTER FAN-IN, 

BITS 10-15 


F TRANSLATIONS 


Q REGISTER, 

BITS 8-15 

Q REGISTER FAN-OUT, 


Y REGISTER FAN-OUT, 
BITS 7-14 


X REGISTER FAN-OUT, 
f BITS 0-4 


A REGISTER FAN-OUT, 
f BITS 0-5 


Q REGISTER FAN-OUT, 
BITS 12-15 
MASK a INTERRUPT REG. 


Y REGISTER CONTROLS If: 


ADR FAN-OUT a 
ADDER P 


X REGISTER FAN-OUT, 
BITS 12-15 

RAW CLOCK FAN-OUT, 
too a t25 


ADDRESS CONTROL I 


TIMING CHAIN (H04-H07) 


K X50 TIME FAN-OUTS 


A REGISTER FAN-OUT, 


1? A REGISTER CONTROL 


F REGISTER CONTROL 


ROP n, STon a RNi ffs — 


ROP I a STO I FFS I5 


MASK a INTERRUPT REG. 


INTERRUPT CONTROL 

Q a MASK REGISTER 
CONTROLS 

INTERRUPT PRIORITY 
BITS 8-15 

INTERRUPT PRIORITY 
BITS 0-7 


GENERAL FAN-OUTS 


REGISTER CLEAR CONTROLS] 


OVERFLOW FAULT FF 


5 SKIP TRANSLATIONS 


STORAGE INTERFACE 


REPLY B REJECT 


SKIP a I/O CONTROL 


BANK 4 SENSE AMPS 
BITS 0-5 


GQ 


O 


O 


UJ 





MAINTENANCE 





AA 101 & 1704 


PREVENTIVE MAINTENANCE INDEX 


Level 1 
Level 2 
Level 3 


Weekly 
Monthly 
6 Months 


LEVEL 
3 2 1 

ITEM 

PREVENTIVE MAINTENANCE 


0. 1 

Preliminary Information 


2, 1 

Clean Air Filters 

X 

2.2 

Check Logic Voltages 

X 

2.3 

Check Indicators 

X 

2.4 

Check Console Controls 

X 

2.5 

Run Diagnostics (Margins Applied) 

X 

2.6 

Check Logic Voltages 

X 

3. 1 

Perform Shock Testing (Memory Stacks 
and Sense Amps) 

X 

3.2 

Check Indicators 

X 

3.3 

Check Emergency Off - On 

X 

3.4 

Run Diagnostics (Logic Voltage 
Margins Applied) 

X 

3. 5 

Perform Shock Testing 


^Level 1 if necessary. 


155 


Rev AH 







PRELIMINARY INFORMATION 


0 . 1 


MARGIN TABLE 


CONDITIONS 

LOGIC VOLTAGE 

DRIVE 

INHIBIT 

CLOCK 

FREQUENCY 

+6 

-6 

1 

Normal 

Normal 

Normal 

Normal 

Normal 

2 

+10% 

+10% 

Normal 

Normal 

Normal 

3 

-10% 

-10% 

Normal 

Normal 

Normal 

4 

Normal 

Normal 

Normal 

Normal 

+10% 

5 

Normal 

Normal 

Normal 

Normal 

-10% 


NOTES 

1. Where level 2 or level 3 PM procedures overlap 

level 1 or level 2 procedures, only the highest 
level procedures need be performed. 

2. Shock testing (Item 2.1) should be performed 
using the standard AMP insertion tool with the 
special nylon shock testing tip (P/N 12209308). 


Rev AH 


156 





2 . 1 

CHECK/Conditions 
1. System power on. 


CLEAN AIR FILTERS 


Action 

1. Remove each of the bottom air filters 
from both of the air filter compart- 
ments (base of the 1704). 

2. If the filter is not extremely dirty, it 
may be cleaned with a vacuum cleaner. 
If required, the filter should be washed 
gently in a detergent - water solution. 
Place the filter vertically while washing 
to avoid damaging it. 

3. Replace corroded filters with new 
filters. 

4. Replace the new or clean filter on top 
of the filters still in each filter com- 
partment. 


157 


Rev AH 



2.2 


CHECK LOGIC VOLTAGE 


CHECK/ Conditions Action 

1. System power on. 

+6 VOLT LOGIC SUPPLY 

2. Depress the +6 volt 
button on the memory 
power supply. 

CHECK: Does the percent- 
age meter read 0%? 

Yes No >1. Adjust the +6 volts. 

2. Repeat CHECK. 

-6 VOLT LOGIC SUPPLY 

3. Depress the -6 volt 
button on the memory 
power supply. 

CHECK : Does the percent- 
age meter read 0%? 

Yes No ^ 1. 

2 . 

Go to next item. 


Adjust the -6 volts. 
Repeat CHECK. 


Rev AH 


158 



2.3 


CHECK INDICATORS 


NOTE 

The 1700 Computer Reference Manual explains in 
detail the operation and indication of all console 
switches and bit switches. This manual should be 
readily available for reference while completing 
these CHECKS. In the event that a given switch, 
indicator or display does not perform properly, 
isolate and correct the problem. 


CHECK/ Conditions 


Action 


1. System power on. 


2. While manually opera- 
ting all bit switches and 
display switches, com- 
plete the following: 

CHECK: Do all the bit 
switches set and clear all 
six (6) register displays 
correctly without sticking or 
binding ? 


Yes 


No- 


CHECK: Are all the Drive 
and Inhibit lights on the 
memory stacks lit? 


Yes No 


> 1 / 

Go to next item. 


■> 1. Take appropriate action. 

2. Correct discrepancy. 

3. Repeat CHECK. 


->1. Correct discrepancy. 
2. Repeat CHECK. 


159 


Rev AH 



2.4 


CHECK CONSOLE CONTROLS 


CHECK/ Conditions Action 

1. System power on. 

2. While performing the 
operations listed in Item 
1. 5 (Run Diagnostics; No 
Margins). 

CHECK : Do the console toggle 
switches operate correctly? 

(Reference; 1700 Computer 
Reference Manual) (Reference: 

SMM Manual). 

Yes No > 1. Isolate and correct problem. 

2. Repeat CHECK. 

Go to next item. 


Rev AH 


160 



RUN DIAGNOSTICS (MARGINS APPLIED) 


NOTE 

Use an accurate D, C. Voltmeter when setting 
margins. On a rotational basis, run all operational 
tests under all conditions as set forth below, such 
that all conditions are covered at least once a month. 

DO NOT PERFORM MARGIN TEST WHILE COMPUTER 
IS ACTIVELY MONITORING ANY PROCESS CONTROL 
FUNCTION. 

TABLE 1 


1. 

SMM17 

Command Test 

(3 Passes) 

2. 

SMM17 

Memory Test 

(3 Passes) 

3. 

Random Protect Test 

(1 Pass) 


CHECK/ Conditions 

1. System power on. 

2. With logic voltages at 
condition 1 (see margin 
table; item 0. 1, Preliminary 
information). 


3. Set margins at condition 2 
(see margin table). 


4. Set margins at condition 3 
(see margin table). 


Action 


1. Run all tests in Table 1 and - 

2. Correct any errors. 

1. Run all tests in Table 1 (excluding the 
memory test) and - 

2. Correct any errors. 

1. Run all tests in Table 1 (excluding the 
memory test) and - 

2. Correct any errors. 


161 


Rev AH 



2. 5 (Continued) 


I 


CHECK/ Conditions Action 

5. Determine the best operating 
point for each memory stack, 
as per the procedure in 
revision E of the 1700 
Maintenance Manual, 

NOTE 

Step 5 may be omitted if previously 
performed, and if the margins in 
Step 6 have not deteriorated from 
those found previously. 

CHECK; Does each stack have at 
least 1. 0 volt drive swing at the 
best operating point? 

Yes No > 1. Correct by replacing defective module 

or stack. 

6. After the stacks have been 
adjusted to their best opera- 
ting point, determine the 
mass memory margins by 
varying the mass memory 
pots while running the worst 
pattern of the 1700 SMM 
memory test. Record these 
margins (from the meter on 
the power supply) for future 
reference. 


Rev AH 


162 



2.6 


CHECK LOGIC VOLTAGES 


CHECK/ Conditions Action 

1. System power on. 

2. Ensure that the +16 volt 
memory bus bar - is at 
least +16 volts. 

3 . Ensure that the +8 volt 
memory bus bar - is at 
least +8 volts. 

4. Use your most accurate D.C. 

Voltmeter to check the +6 
volt logic voltage setting. 

Ensure that the percentage 
meter says 0% when the 
actual measured voltage is 
+6.0 volts. 

CHECK; Is the percentage meter 

zeroed with a +6 volt setting? 

Yes No > 1, To zero the percentage meter, remove 

the memory power supply access panel. 
Adjust the correct potentiometer on the 
printed circuit board (upper left hand 
corner of the power supply). 

2. Replace access panel. 

3. Repeat CHECK 

5. Use your most accurate D.C. 

Voltmeter to check the -6 volt 
logic voltage setting; Ensure 
that the percentage meter says 
0% when the actual measured 
voltage is -6.0 volts. 


163 


Rev AH 



2.6 (Continued) 


CHECK/Conditions 

CHECK: Is the percentage meter 
zeroed with a -6 volt setting? 

Yes No 


V 

Go to next item. 


Action 


■>1. To zero the percentage meter: Remove 
the memory power supply access panel. 
Adjust the correct potentiometer on the 
printed circuit board (upper left hand 
corner of the power supply). 

2. Replace access panel. 

3. Repeat CHECK. 


Rev AH 


164 



PERFORM SHOCK TESTING 


3. 1 


NOTE 

DO NOT PERFORM SHOCK TEST WHILE COMPUTER 
IS ACTIVELY MONITORING ANY PROCESS CONTROL 
FUNCTION. 

CHECK/ Conditions Action 

!• System power on. 

2. Load and execute the SMM17 
Memory Test. Select para- 
meters to test one stack at a 
time. 

3. While monitoring test, shock 
test the selected memory sense 
amp module and memory stack 
(use shock test tip). 

CHECK: Is test still running? 

Yes No >1. Repair or replace shock sensitive 

module or stack. 

2. Repeat CHECK. 

4. Go back to Step 2 and select 
the next stack. 


165 


Rev AH 



3.2 


CHECK INDICATORS 


CHECK/ Conditions Action 

1. System power on. 

OVERFLOW, PROGRAM PROTECT, PARITY ERROR 

2. All console switches to neutral. 

Set the ENTER switch. Enter 

in the X register. 

3. Place computer in run. 

Do not step or clear the 
computer until Step 6 has 
been completed. 

4. Return ENTER switch to 
neutral. 

CHECK : Did the overflow light 
come on? 

Yes No >1. Isolate and correct problem. 

2. Repeat CHECK. 

5. Set the ENTER switch again. 

Set the PROGRAM PROTECT 
switch. 

CHECK : Is the Program Protect 
Fault Light Lit? 

Yes No ^ 1. Isolate and correct problem. 

2. Repeat CHECK. 

Y 

6. Return ENTER switch to 
neutral. 

Return the PROGRAM 
PROTECT switch to neutral. 


Rev AH 


166 



3.2 (Continued) 


CHECK/ Conditions Action 

Ground B21, test point 6. 

CHECK : Is the Parity Error 
Light Lit? 

Yes No >1. Isolate and correct problem. 

2. Repeat CHECK. 

V 

INSTRUCTION, INDIRECT ADDRESS, STORAGE INDEX, OPERAND 


1 . 


Enter C501 
memory at 
Enter 0000 
memory at 
Enter 0000 
memory at 


(16) 
P = 


in 

0000 . 


(16) 
P = 


in 

0001 . 


(16) 
P = 


in 

OOFF. 


2. Master clear. 


3. All toggle switches in 
neutral. 


CHECK: Are the Instruction and 
Program Protect Bit lights lit? 


Yes No 

4. Depress the STEP switch 
once. 

CHECK : Does the INDIRECT 
Address light come on? 

Yes No 

5. Depress the STEP switch 
once. 


^ 1. Isolate and correct problem. 
2. Repeat CHECK. 


1. Isolate and correct problem. 

2. Repeat CHECK. 


167 


Rev AH 



3.2 (Continued) 


CHECK/ Conditions 

CHECK ; Does the Storage Index 
light come on? 


Yes 


No 


6. Depress the STEP switch 
once. 

CHECK : Does the Operand light 
come on? 


Yes 


No 


Go to next item. 


Action 


->1. Isolate and correct problem. 
2. Repeat CHECK. 


->1. Isolate and correct problem. 
2. Repeat CHECK. 


Rev AH 


168 



3.3 


CHECK EMERGENCY OFF-ON 


CHECK/ Conditions Action 

1. System power on. 

2. No program in operation. 

1. Verify that the EMERGENCY OFF 
switch works correctly. 


169 


Rev AH 



3.4 


RUN DIAGNOSTICS (LOGIC VOLTAGE MARGINS APPLIED) 


NOTE 

Use an accurate D. C. Voltmeter when setting margins. 
On a rotational basis, run the Command Test under 
the conditions listed, such that all conditions are 
covered at least once each six months. 

DO NOT PERFORM MARGIN TESTS WHILE COMPUTER 
IS ACTIVELY MONITORING ANY PROCESS CONTROL 
FUNCTION. 

CHECK/ Conditions Action 

1. System power on. 

2. Load and execute the SMM17 
Command Test (three passes for 
each of the conditions listed). 

a. Condition 2 

(Ref. Margin Table: 

Item 0. 1, preliminary 
information) 

b. Condition 3 

(Ref. Margin Table) 

c. Condition 4 

(Ref. Margin Table) 

di Condition 5 

(Ref. Margin Table) 

CHECK : Does the Command Test 
successfully run three passes 
under each of the four marginal 
conditions ? 

Yes No >1. Isolate and correct 

2. Repeat CHECK. 

Go to next item. 


Rev AH 


170 



3.5 


PERFORM SHOCK TESTING 


NOTE 

Schedule shock testing on a rotational basis so that 
each module is completed once each six months. 

CHECK/ Conditions Action 

1. System power on. 

2. D.C. Chassis Voltages 

a. +6 volts 

b. “6 volts 

3. Storage Drive Margins 
a. Normal 

4. Clock frequency 
a. Normal 

5. Load and execute the 
SMM17 Command Test 
with parameters selected 
for 100 operands. 

6. While monitoring test - 
Shock test each module 
(use shock test tip). 

CHECK : Does the Command 
Test run successfully? 

Yes No > 1. 

I 2 . 


Isolate and correct. 
Repeat CHECK. 




171 


Rev AH 



3. 5 Continued 


CHECK/ Conditions 

?• Load and execute SMM 
17 program protect test. 

8. While monitoring test, 
shock test each module. 

CHECK: Does Program Protect 
Test run successfully? 

Yes No 

END 


Action 


1. Isolate and correct. 

2. Repeat CHECK. 


Rev AH 


172 



APPENDIX A 


INSTRUCTION FLOW CHARTS 


This appendix contains flow charts that show the steps in execution 
of the following instructions. 


•Shift Instructions 


ARS - A Right Shift 
ALS - A Left Shift 
QRS - Q Right Shift 
QLS - Q Left Shift 

LRS - Long Right Shift (QA Shift, Right) 
LLS - Long Left Shift (QA Shift, Left) 

• Multiply 


MUI - Multiply Integer 
• Divide 


DVI - Divide Integer 



V 


h- CO 
Ll. Z 

I 2 

o a: 
o y 

fs_ Q_ 

o 


Rev AM 


A-2 



Rev AM 


1700 COMPUTER SHIFT OPERATIONS- ALL SHIFTS 


I 











Rev AM A-4 


1700 COMPUTER SHIFT OPERATIONS 

ALL SHIFTS 


Page 3 



47 

,f/>v>,Yes 

Set 

Left 

Shift 

A-T325 


Snut ( — • 

f 


47 1 

No 

Set 



Right 

Shift 

, A-T325 



o — 



11 


Set 

C Cycle 
C-TOO 


SHORT CYCLE 1 PRESENT BECAUSE OF 
SHIFT INSTRUCTION TRANSLATION. 

SCI BLOCKS H03 AND H04 
ENABLES H05 (PAGE 7)* 

11 11 



Set 


Set 

Early B 


B Cycle 

A-T360 


B-TOO 



To 

Page 


S> 


Decrement 

*“^L5 

C-TOO 

1 

. « 

Clear 


Y 


Bits 5, 6 and 8 


C-TOO 




♦SHORT CYCLE 2 PRESENT BECAUSE 
SHIFT CYCLE F/F IS SET. 

SC2 BLOCKS H06 AND HOT, ENABLES 
HOO (PAGE 7) 















Rev AM 


1700 COMPUTER SHIFT OPERATIONS 













Rev AM 


1700 COMPUTER SHIFT OPERATIONS 

A REGISTER SHIFTS 









X 

CO 


< a: 

UJ 


u- I- 
O <0 


ro CD 

LU 


UJ OC 
CD 




A-7 


Rev AM 



Rev AM 


1700 COMPUTER SHIFT OPERATIONS 

Q SHIFTS 

IDENTICAL WITH PAGE 4 OF A SHIFTS BUT WITH 

Q REGISTER 



1700 COMPUTER SHIFT OPERATIONS - QA SHIFTS 


Set 

Adder-»-Q 

C-T50 


Left 


Bit 15 = 1?^ 


Set 

Bit Bucket 
C-TIOO 


Adder -►Q 
C-TlOO 


Clear 

Q-*Adder 

C-TIOO 


Sign 

Extend Q 
C-TIOO 


Clear 
Bit Bucket 
C-TIOO 


Q ^ 
Bit 0 = 1? 


Set 

Bit Bucket 
C-TIOO 


Clear 
Bit Bucket 
C-TIOO 


A -►Adder 
C-TIOO 


Set 

Long Shift 
C-T125 


Set 

Adder-^A 

C-T150 


Yl5=0? 


Clear 

aiift 

Cycle 

C-T150 


Set 

Decrement Y 
C-T150 



Rev AM A- 10 


1700 COMPUTER SHIFT OPERATIONS 

QA SHIFTS 




Rev AM 


1700 COMPUTER SHIFT OPERATIONS 

ALL SHIFTS 





Rev AM A- 12 


1700 COMPUTER 

ALL 


SHIFT OPERATIONS 
SHIFTS 












A-13 


Rev AM 



Rev AM A- 14 


Start 


0 


1700 COMPUTER MULTIPLY OPERATION 

THIS FLOW CHART BEGINS AT T50 OF THE 
LAST B CYCLE OF ADDRESSING 



Positive form of 
multiplier now 
in A. 





-15 Rev AM 


1700 COMPUTER MULTIPLY OPERATION 





H a. 






















Rev AM 


1700 


SHORT CYCLE 1 
C - CYCLE T150 
= NORMAL T250 









Rev AM A- 18 


1700 COMPUTER MULTIPLY OPERATION 



Repeat 
C Cycle 


























1700 COMPUTER MULTIPLY OPERATION 





Rev AM 


1700 COMPUTER MULTIPLY OPERATION 











Q < 


O LlI 
O Q. 
h- O 


Rev AM 


A-22 



-23 Rev am 


1700 COMPUTER DIVIDE OPERATION 

QA MUST CONTAIN THE DIVIDEND BEFORE EXECUTION 
OF A DIVIDE INSTRUCTION . THIS FLOWCHART BEGINS AT 
T50 OF THE LAST B CYCLE OF ADDRESSING. 


> 



Positive form of 
the lower 16 bits 
of the dividend now 
in A. 








Rev AM A-24 


1700 COMPUTER DIVIDE OPERATION 


39 41 41 45 



73 51 39 39 



45 51 11 11 















1700 COMPUTER DIVIDE OPERATION 


U1 





Subtract 





? 1700 COMPUTER DIVIDE OPERATION 

< 

5 > 



Form Quotient Shift A 


47 31 31 49 



Repeat 
C Cycle 


Shift Q 




-27 Rev AM 


1700 COMPUTER DIVIDE OPERATION 











Rev AM A-28 


1700 COMPUTER DIVIDE OPERATION 




Final Quotient 
now in A. 








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CONTROL DATA 1700 COMPUTER SYSTEM 


Diagrams and Circuit Description CE Manual 


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REVISION. 


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